Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-23
2004-02-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C712S036000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06694489
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and more specifically to a improved test interface on a configurable processor system.
BACKGROUND OF THE INVENTION
The Joint Test Action Group (JTAG) interface provides access to a configurable system-on-chip for test and debugging functions. The JTAG interface is a serial port, which can be connected to a monitoring/test computer via a serial cable.
FIG. 1
illustrates an IEEE 1149.1 specification JTAG interface
100
. Test data is input at the test data input (TDI)
110
. Three registers are connected in parallel: The bypass register
120
is a single bit register and passes data directly from the TDI
110
to the test data output (TDO) multiplexer
150
. The boundary scan register
130
provides the capability to scan or place data on every I/O pin of the configurable system-on-chip being tested. The instruction register
140
provides the instruction to select one register to be connected between the TDI
110
and TDO
150
.
IEEE 1149.1 specification defines the standard, basic functions of the JTAG interface. The IEEE 1149.1 specification requires only the boundary scan register, the bypass register and the instruction register. The IEEE 1149.1 specification is hereby incorporated by reference in its entirety, for all purposes. The IEEE 1149.1 specification interface provides only limited utility in and of itself. To provide additional utility, the IEEE 1149.1 specification also allows proprietary extensions or additional capabilities as long as the basic IEEE 1149.1 specification remains supported.
A computer configurable system-on-chip
200
block diagram of one example of an extended, proprietary JTAG incorporating an extended JTAG interface is illustrated in FIG.
2
. The JTAG
205
provides a dedicated, four-pin serial interface
208
with many uses. The JTAG unit
205
can access all addressable system resources by becoming the bus master on the internal CSI bus
260
. Serving as a bus master, the JTAG unit
205
converts serial bit streams into parallel registers whose contents are placed on the address, data and command buses to emulate CSI bus transactions. The JTAG unit
205
can also directly accesses internal CPU
220
registers and CSL
215
configuration data with visibility to functions not accessible from application programs.
FIG. 2
shows the JTAG as a bus master. A multi-master/multi slave internal system bus
260
connects to several building blocks including a CPU
220
, DMA unit
240
, memory devices
230
, and peripherals. The JTAG unit
205
, as a bus master, is capable of requesting a bus access. When the JTAG unit
205
gains control over the internal bus
260
, it is capable of accessing any addressable element connected on the system. A detailed description of the operation of the JTAG unit
205
is provided in Winegarden et al., PCT application WO 00/22546. PCT application WO 00/22546 is hereby incorporated by reference for all purposes.
A computer
210
acting as an external tester/debugger can interface with the CPSU device
200
via the JTAG interface
205
, using a cable connected between the computer and the target board as shown in FIG.
2
.
The JTAG unit
205
can serve as a bus slave when interacting with the DMA unit
240
. First the JTAG unit
205
becomes master on the CSI bus
260
, programs the DMA unit
240
to transfer data to or from the JTAG unit
205
, and then relinquishes the CSI bus
260
to the DMA unit
240
. After configuring the DMA unit
240
, the JTAG unit
205
interfaces with the DMA unit
240
as a slave device using the DMA unit's
240
request and acknowledge signals. Unfortunately, using the DMA unit
240
in this manner conflicts with many software functions that may be running on the system
200
being tested. This requires users to modify their software to work around this use of the DMA
240
.
FIG. 3
illustrates a block diagram of the JTAG
205
internal components. The IEEE 1149.1 specification is supported through the 1-bit bypass register
305
, the boundary scan register
310
, the 4-bit instruction register
320
, TDI
380
, multiplexer
390
and TDO
395
. Additional registers include: The device identification (ID) register
330
is a 32 bit register for storing a manufacturer's identification information such as part number, serial number, software revision number, etc. The master register
340
provides several proprietary data transfer functions, which are described in more detail below. The bustat register
350
is an 11-bit register that captures various proprietary status signals from different parts of the configurable system-on-chip being tested. The DMADAT register
360
is a 9-bit register that provides data transfer to and from the DMA unit
240
when the JTAG
205
asserts control over the DMA unit
240
. The scan chain register
370
applies and captures internal scan patterns during a manufacturing test.
The master register
340
provides several functions. The master register
340
can transfer any one of five different lengths of data, depending on the instruction. First, in a Mwrite_long instruction, during a capture state, master register
340
captures 41 bits from the configurable system-on-chip under test. During a subsequent shift state, the 41 bits plus a MwL_READY bit are shifted out to the TDO
395
. The MwL_READY bit is the first bit shifted out. Second, in a Mwrite instruction, during a capture state, master register
340
captures 25 bits from the configurable system-on-chip under test. During a subsequent shift state, the 25 bits plus a Mw_READY bit are shifted out to the TDO
395
. The Mw_READY bit is the first bit shifted out. Third, in a Mread_long instruction, during a capture state, master register
340
captures 41 bits from the TDI
380
. During a subsequent shift state, the 41 bits are shifted out to the configurable system-on-chip under test. Fourth, in a Mread instruction, during a capture state, master register
340
captures 25 bits from the TDI
380
. During a subsequent shift state, the 25 bits are shifted out to the configurable system-on-chip under test. Fifth, in a Mverify instruction, during a capture state, master register
340
captures 9 bits from the configurable system-on-chip under test. During a subsequent shift state, the 9 bits plus a Mv_READY bit are shifted out to the TDO
395
. The Mv_READY bit is the first bit shifted out.
In each master register
340
instruction the precise corresponding number of bits in the bit chain must be shifted into or out of the master register
340
to shift useable data into or out of the master register
340
. This precise requirement of bit chain length is referred to as continuous write-in or read-out during the Mwrite_long, Mwrite, and Mverify instructions the corresponding READY bit (MwL_READY, Mw_READY and Mv_READY, respectively) is the first bit shifted out of the master register
340
. The READY bit indicates that the previous master-bus operation has been successfully completed and the data represents the results of the previous master-bus operation. The READY bit is used by the tester/debugger
210
to confirm that the previous master-bus operation had occurred. If the tester/debugger
210
does not receive a valid READY bit, then the tester/debugger
210
disregards the data received and resends the previous master-bus instruction. Because the READY bit determines the validity of the data received by the tester/debugger
210
, it is very important that the READY bit be accurately transferred to the tester/debugger
210
so as to reduce the occurrence of resending the previous master-bus instruction and resulting data.
The serial interface between the tester/debugger
210
and the JTAG
205
is limited to approximately 100 kHz. The excessive instruction and resulting data resends consume excessive bandwidth in the serial interface between the JTAG
205
and the external tester/debugger
210
. The excessive instruction and resulting data resends cause additional time delays in testing the configurable system-on-chip.
Allegrucci Jean-Didier
Case Jerry
Do Thuan
Smith Matthew
Triscend Corporation
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