Test interface circuit and semiconductor integrated circuit...

Details Test interface circuit and semiconductor integrated circuit... Test interface circuit and semiconductor integrated circuit...

2000-12-21

2002-06-11

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230080, C365S233100

Reexamination Certificate

active

06404684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test interface circuit and a semiconductor integrated circuit device using the same, and particularly relates to a test interface circuit for externally and directly testing a logic-merged memory as well as a semiconductor integrated circuit device including the same.
2. Description of the Background Art
In a system LSI such as a logic-merged DRAM, in which a logic such as a processor or an ASIC (Application Specific Integrated Circuit) and a Dynamic Random Access Memory (DRAM) of a large storage capacity or the like are integrated on a common semiconductor chip (semiconductor substrate), the logic and the DRAM are interconnected via an internal data bus of multiple bits from 128 bits to 512 bits for achieving a data transfer rate faster by one, two or more orders than that of a general-purpose DRAM. The DRAM and the logic are interconnected via internal interconnection lines, which are much shorter in length and smaller in parasitic impedance than on-board interconnection lines. Therefore, charge/discharge currents of the data bus can be significantly reduced, and signal transfer can be performed at high speed. Since the logic is connected to the DRAM via internal interconnection lines, external pin terminals of the logic can be smaller in number than those of the type that a general-purpose DRAM is externally attached to the logic. Because of the foregoing reasons, the DRAM-embedded system LSI significantly contributes to improvement of a performance of an information device handling a large amount of data, e.g., for three-dimensional graphics, image or audio processing.
In the logic-merged DRAM, only the logic is coupled to pin terminals via pads. Therefore, a function test of the embedded DRAM must be performed via the logic. However, the logic performs control for carrying out the test, and therefore has to bear a large load. Further, such operations are required that an instruction for performing a function test of the DRAM is externally applied to the logic, a control signal for performing the function test is applied from the logic to the DRAM, and a result of the test must be read out via the logic. Thus, the function test of DRAM is executed via the logic so that tests of, e.g., an operation timing margin of the DRAM cannot be performed accurately. Further, from a viewpoint of a program capacity, the logic can generate only a limited number of test patterns so that the test cannot be performed sufficiently, and it is difficult to sufficiently ensure the reliability of the DRAM. As a gate scale of the logic increases, the probability of occurrence of a failure in the logic itself increases so that the reliability of the memory test lowers.
Accordingly, it becomes necessary to carry out externally and directly the test on the DRAM via a dedicated test device.
FIG. 13
schematically shows a structure of a DRAM-embedded system LSI in the prior art. In
FIG. 13
, the system LSI includes a large scale logic LG which is coupled to an external pin terminal group LPGA and executes instructed processing, an analog core ACR which is coupled between large scale logic LG and an external pin terminal group APG and processes analog signals, a DRAM core MCR which is coupled to large scale logic LG via internal interconnection lines, and stores data required by large scale logic LG, and a test interface circuit TIC which isolates large scale logic LG from DRAM core MCR, and couples an external memory tester to DRAM core MCR via a pin terminal group TPG in a test mode. DRAM core MCR receives a power supply voltage VCC via a power supply pin terminal PST.
Analog core ACR includes a phase locked loop circuit (PLL) generating an internal clock signal, an analog-to-digital converter for converting an externally applied analog signal to a digital signal, a digital-to-analog converter for converting a digital signal sent from large scale logic LG to an analog signal for outputting it.
DRAM core MCR is a clock-synchronous memory (SDRAM).
Large scale logic LG includes a memory control unit for executing processing, e.g., of image/audio information and controlling access to DRAM core MCR.
By providing test interface circuit TIC as shown in
FIG. 13
, DRAM core MCR can be completely isolated from the logic, and can be directly accessed via external pin terminal group TPG, and therefore DRAM core MCR can be directly and externally controlled, and can be externally monitored. The test performed in this manner is called a direct memory access test. By providing test interface circuit TIC, a conventional memory tester can be utilized, and the test substantially the same in contents as that of a general-purpose DRAM (SDRAM) can be carried out.
FIG. 14
shows a structure of a test interface circuit TIC shown in
FIG. 13 and a
portion related to it. In
FIG. 14
, pin terminal group TPG includes a pin terminal receiving a test clock signal TCLK, a pin terminal receiving a test address TAD designating a memory cell in DRAM core MCR to be accessed in the test mode, a pin terminal receiving test input data TDin in the test mode, and a pin terminal receiving test data TDout from test interface circuit TIC in the test mode. Test input data TDin applied to test interface circuit TIC and test data TDout sent from test interface circuit TIC have a bit width of, e.g., 8 bits similar to data in the general-purpose DRAM.
Test interface circuit TIC includes: a latch and command decoder
1
which takes in a test control signal TCMD, test address TAD and test input data TDin applied to pin terminal group TPG, decodes test control signal TCMD into an internal command to be issued to DRAM core MCR, and performs operations such as expansion of test input data TDin of an 8-bit width to write data of 256 bits; a mode register
2
which stores information such as a column latency of DRAM core MCR; a CA shifter
3
which shifts a read data select signal RD_S applied from latch and command decoder
1
in accordance with column latency information stored in mode register
2
and others; a 256-to-8 select circuit
4
which selects data of 8 bits from test read data TIFDout of 256 bits read from DRAM core MCR in accordance with read data select signal RD_S read from CA shifter
3
.
As test peripheral circuits, there are arranged: a selector
5
which is responsive to a test mode instructing signal TE to couple DRAM core MCR selectively to the large scale logic and test interface circuit TIC; a gate circuit
6
which receives clock signal CLK applied from the large scale logic in the normal operation mode and test clock signal TCLK applied in the test mode, and applies a clock signal to DRAM core MCR; and a gate circuit
7
which transmits read data RD of 256 bits read from DRAM core MCR to test interface circuit TIC when test mode instructing signal TE is active. Read data RD of 256 bits read from DRAM core MCR is applied to the large scale logic without passing through selector
5
. This is for the purpose of applying the read data fast to the large scale logic in the normal operation mode.
DRAM core MCR is a clock-synchronous DRAM (SDRAM), and operates in synchronization with the clock signal to take in data/signal applied from selector
5
and output read data RD.
Operations of the test interface circuit shown in
FIG. 14
will now be described with reference to a timing chart of FIG.
15
.
As shown in
FIG. 14
, DRAM core MCR transfers write data INDin and read data RD through separated paths, respectively. Likewise, test input data TDin and test data TDout are transferred through different test pin terminals in the test operation, respectively.
Test control signals TCMD including signals /RAS, /CAS, /WE and others are decoded to attain a state for reading out data from DRAM core MCR, or applying a read command READ to DRAM core MCR. Test control signal TCMD applied in a clock cycle #
1
is decoded by latch and command decoder
1
, and the result of decoding is applied as read command READ from test interface circuit TIC to DRAM

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