Test head Hifix for semiconductor device testing apparatus

Details Test head Hifix for semiconductor device testing apparatus Test head Hifix for semiconductor device testing apparatus

2002-12-12

2004-03-23

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S754090

Reexamination Certificate

active

06710590

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and, more particularly, to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus.
2. Description of the Related Art
Semiconductor device testing apparatuses test various types of semiconductor devices including integrated circuits. Integrated circuits are tested to ensure that they will function properly in the consumer domain. Because integrated circuits must be individually tested, it is desirable that a semiconductor device testing apparatus accurately test integrated circuits at a low manufacturing test cost.
During the fabrication process, integrated circuits arc tested in wafer form and in packaged form. In wafer form, a probe card is used to establish a temporary electrical contact between the integrated circuit to be tested (known as the device-under-test or DUT) and the semiconductor device testing apparatus (known as automatic test equipment or ATE). After completion of testing in wafer form, the integrated circuit is packaged and tested. Testing in packaged form includes a performance board or loadboard as the interface between the DUT and the ATE. The loadboard is a multi-layer printed circuit board that is mounted directly on the ATE. The DUT is inserted into a socket on the loadboard to establish electrical contact for testing.
FIG. 1
illustrates a conventional ATE system for testing an integrated circuit in packaged form. A tester
1
generates test signals which are transmitted to a test head
2
through cables
3
. The test head
2
, as shown by the cut-away view, houses a plurality of printed circuit boards or pin cards
4
. The test signals are transmitted from the pin cards
4
to contact pins or pogo pins
5
. The contact pins are represented schematically in
FIG. 1
by arrows. It should be noted that the number of contact pins is much greater than what is illustrated in FIG.
1
and that the various elements of the ATE system in
FIG. 1
are not drawn to scale.
The pogo pins
5
extend through the top surface
6
of the test head
2
, known as the test head Hifix. The pogo pins
5
are spring-loaded and press against the loadboard
7
to establish electrical contact for testing. The loadboard
7
is positioned for such contact by an assembly or locking mechanism
10
that is directly placed on the test head Hifix
6
The loadboard
7
is in turn a mount for socket
8
. The DUT
9
in packaged form is inserted into socket
8
to establish electrical contact for testing. Thus, the test signals are transmitted from the tester
1
to the DUT
9
through the pin cards
4
, contact pins
5
, loadboard
7
and socket
8
. The resulting signals from the DUT
9
are received by the tester
1
for evaluation through the same elements.
As illustrated in
FIG. 1
, the assembly
10
, the loadboard
7
, the socket
8
and the DUT
9
rest on the test head Hifix
6
. The test head chassis generally includes a square or rectangular plate as the test head Hifix for covering the pin cards and cables within the test head. It is secured to the test head by screws
11
along the border of the chassis (only two screws are shown in FIG.
1
). If maintenance or repair is required within the test head, the test head chassis must be entirely disassembled in order to access the parts within the test head. Disassembly requires undoing all of the screws and removing the entire Hifix, assembly and loadboard from the test head. It also requires disconnecting the pogo pins attached to pin cards from the assembly. This entire procedure is time consuming and increases the time for maintenance or repair, thereby increasing manufacturing test cost.
Moreover, the test head chassis must be entirely disassembled regardless of the reasons for the maintenance or repair. Minor maintenance or repairs requires the same disassembly procedure as for a major maintenance or repair. As a result, even for minor maintenance and repairs, the test head becomes completely inoperable thereby stopping the testing of the DUT and increasing manufacturing test cost.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device testing apparatus that overcomes the above limitations. The semiconductor device testing apparatus of the present invention includes a test head Hifix that does not require disassembly for maintenance or repair of the semiconductor testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved to provide access to pogo pins and pin cards without disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.
The semiconductor device testing apparatus of the present invention allows various parts of the apparatus such as the pin cards and cables to be easily accessed for maintenance or repair. For example, electrical measurements can be made on pin cards to determine a malfunction without complete disassembly. By avoiding complete disassembly, the semiconductor device testing apparatus can also remain operational for testing of the DUT, thereby reducing manufacturing test cost. Indeed, the design and continued operability of the semiconductor device testing apparatus of the present invention allows for other measurement instruments to be easily connected for testing of the DUT.
These and other features and advantages of embodiments of the present invention will be apparent to those skilled in the art from the following detailed description of the embodiments of the invention, when read with the drawings and the appended claims.


REFERENCES:
patent: 4160207 (1979-07-01), Haines
patent: 4667155 (1987-05-01), Coiner et al.
patent: 4862075 (1989-08-01), Choi et al.
patent: 5001422 (1991-03-01), Dahlberg et al.

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