Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-04
2001-10-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C324S537000
Reexamination Certificate
active
06308300
ABSTRACT:
1. FIELD OF THE INVENTION
This invention relates to a method of testing analog and mixed analog /digital circuits in which the analog circuit defined as a directed circuit graph is partitioned and certain partitions between a circuit input and analog fault are inverted before being simulated in order to generate test waveforms which can be applied to the circuits to be tested.
2. DESCRIPTION OF THE RELATED ART
Mixed signal devices are being increasingly used for wireless communication, data acquisition and processing and other applications of analog and digital processing. The use of analog components within digital systems has necessitated testing of analog circuits to determine faults of the circuit. Accordingly, it has become a problem in the industry to test analog and mixed signal devices having analog and digital circuits.
Conventional solutions to testing of analog and mixed signal devices have been achieved by sensitivity analysis of models of the devices to be tested. Analog fault models of “catastrophic” faults on which there is a sudden and large deviation in a component value resulting in shorted and open circuits and “parametric” faults in which a component value varies with time or environment, causing potentially unacceptable deviations in the circuit behaviors have been described in Duhamel et al,
Automatic Test Generation Techniques for Analog Circuits and Systems: A Review,
IEEE Transactions on Circuits and Systems, Vol. CAS-26, No. 7: 411-440 July 1979. Analog test methods described include estimation methods, topological methods, taxonomical methods and linear system methods.
An analog circuit efficient fault simulation for mapping the circuit and circuit level faults to the discrete domain is described in Nagi et al.
Discretized Analog Fault Simulator
ACM/IEEE Design Automation Conference, pp. 592-599, June, 1993. Bilinear transformations map circuit equations into the Z domain. A first module performs a good circuit simulation while a second module processes the fault list and maps each fault into the discrete domain. A circuit description is given as input to a simulator. The simulator can use a simulation package, such as the simulation package with integrated circuit emphasis, SPICE. A preprocessor parses the input to extract connectivity information into an internal graph data structure. A transfer function is determined for each operational amplifier (op amp) block of the circuit. A signal flow graph is constructed and the transfer functions are used to obtain appropriate weights on the edges of the signal flow graph. Since the obtained signal flow graph may not be in the form that directly results in state equations, because the state equations are first order differential equations while the transfer functions can be second or higher order, the op amp faults are first modeled in the S-domain before mapping them to the Z-domain. The resulting equations are simulated for any given input. The above-described simulation approach has the drawback of defining the effect of the fault on the circuit outputs, but not defining the analog test pattern needed to test the circuit.
U.S. Pat. No. 5,831,437, issued to the inventors of this disclosure, describes a method and apparatus for generating test patterns to test analog or mixed circuits. A signal flow graph of the analog circuit is determined. The signal flow graph is inverted and reverse simulated with good and bad outputs to determine component tolerances of the circuit given circuit output tolerances. The inverted signal flow graph is backtraced from analog outputs to obtain analog input sinusoids which justify the analog outputs. This patent has the limitation of not being capable of testing for transistor faults.
It is desirable to provide a simplified method for test generation of analog and mixed signal devices, in particular for testing analog transistor faults.
SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus for testing analog and mixed analog and digital circuits in which test waveforms are generated for testing the analog circuit. The analog circuit can be represented by a directed circuit graph. The directed circuit graph represents nodes of components of the circuit under test connected by directed edges for components having inputs or outputs which effect other components and undirected edges for components in the circuit that are bidirectional. For example, undirected edges are assigned to bidirectional elements such as resistors and capacitors and directed edges are assigned to transistors. The directed graph is partitioned into partitions that carry a signal from the primary inputs toward the primary outputs in the circuit under test. Feedback and local feedback are captured in a single partition. The partition of a faulty component is determined and the operating point of the partition is established to activate the fault. The fault effects on the transfer function of each partition are determined by fault sensitization and fault effect propagation.
In a preferred embodiment fault effects are obtained by determining system equations for each partition of the directed circuit graph. Preferably, for each partition having a faulty component or being between a circuit input and the faulty component, the analog system equations are partially inverted during simulation to invert inputs or outputs, thereby determining the analog waveform through simulation that is needed to produce a specified output waveform. Partitions after the partition including the faulty component are non-inverted in the simulation. Tolerances of the analog components can be defined in terms of the analog circuit output deviations with good and bad outputs of the circuit. Analog input test waveforms are obtained by simulating or solving the system equations. A good output is defined as an output within the voltage or current tolerance and a bad output is defined as an output that is outside the voltage or current tolerance. Input analog test waveforms are determined for the good output and bad output conditions and all node voltage and voltage source waveforms using transient waveform analysis. The generated input test waveforms can be applied to the analog circuit for testing the circuit. Monte Carlo analysis is preferably used during the simulation for determining a family of analog test waveforms throughout the analog circuit under test in the time domain. A Fast Fourier Transform is used to transform the analog test waveforms for good and bad outputs into the frequency domain. A determination is made from the sum of the frequency values of the good and bad test waveforms as to whether the sum value is within the tolerance for an analog circuit without a fault.
The present invention has the advantage of expeditiously and accurately testing analog circuits. Further, the method provides the capability of testing for DC transistor biasing faults, variations in transistor gain and variations in threshold voltages that determine switching of the device between operating nodes. DC transistor operating biasing faults mean that some transistor in the circuit is operating in the wrong mode which can lead to: non-linear responses of the faulty circuit when the good circuit would exhibit linear responses; excessive power consumption of the circuit; and clipping of the analog circuit output response. The method also provides the ability to compute component tolerances for analog circuits based on a particular analog test waveform and on deviation allowed at the analog circuit output.
The invention will be more fully described by reference to the following drawings.
REFERENCES:
patent: 5202639 (1993-04-01), McKeon et al.
patent: 5383194 (1995-01-01), Sloan et al.
patent: 5422891 (1995-06-01), Bushnell et al.
patent: 5831437 (1998-11-01), Ramadoss et al.
J. Vlach et al., Simulation of Networks with Inconsistent Initial Condition, May 1993 IEEE International Symposium on Circuits and Systems, pp. 1627-1630.*
R. Ramadoss et al., Test Generation for Mixed Signal Devices using Signal Flow Graphs,
Bushnell Michael L.
Ramadoss Rajesh
Mathews, Collins Shepherd & Gould P.A.
Rutgers University
Smith Matthew
Thompson A. M.
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