Test for weak SRAM cells

Details Test for weak SRAM cells Test for weak SRAM cells

2007-04-03

2007-04-03

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000

Reexamination Certificate

active

10548340

ABSTRACT:
A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step104), the bit lines are then shorted together (step106), the word lines are disabled (step108) and the bit lines are released (step110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step114).

REFERENCES:
patent: 7133319 (2006-11-01), Wuu et al.
patent: 2004/0246797 (2004-12-01), Jeung et al.
patent: 2006/0187724 (2006-08-01), Pineda De Gyvez et al.

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