Test enable control for built-in self-test

Details Test enable control for built-in self-test Test enable control for built-in self-test

1998-01-09

2000-01-11

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

365201, 371 211, G11C 700

Patent

active

060143363

ABSTRACT:
A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.

REFERENCES:
patent: 5210864 (1993-05-01), Yoshida
patent: 5224103 (1993-06-01), Ligthart et al.
patent: 5479414 (1995-12-01), Keller et al.
patent: 5633813 (1997-05-01), Srinivasan
patent: 5758058 (1998-05-01), Milburn
patent: 5883843 (1999-03-01), Hii et al.

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