Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2007-09-05
2010-10-05
Cao, Phat X (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C324S765010, C324S762010, C324S762010
Reexamination Certificate
active
07807997
ABSTRACT:
Two TEGs are used for acquiring FET capacity. A first TEG includes a first base section of the same shape and same dimensions as a gate electrode of the FET whose capacity is to be acquired, and a first additional section added at one end of the first base section. A second TEG includes a second base section of the same shape and same dimensions as the first base section, a second additional section having the same shape and same dimensions as the first additional section and added to one end of the second base section, and a third additional section having the same shape and same dimensions as the second additional section and added to the other end of the second base section. The capacity between the body and source or between the body and drain of the FET whose capacity is to be acquired is estimated from the difference in capacity between the body and source or between the body and drain of the first TEG and second TEG.
REFERENCES:
patent: 2004/0256676 (2004-12-01), Hirotsu et al.
patent: 2000-216258 (2000-08-01), None
patent: 2003121489 (2003-04-01), None
patent: 2004-253564 (2004-09-01), None
Cao Phat X
Garrity Diana C
Oki Semiconductor Co., Ltd.
Rabin & Berdo P.C.
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