Test element group structure

Details Test element group structure Test element group structure

2002-09-11

2004-03-16

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S062000, C324S765010, C324S762010

Reexamination Certificate

active

06707064

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit fabricating technology and, more particularly, to a semiconductor device formed on a semiconductor wafer having a scribe line area between chip areas.
BACKGROUND OF THE INVENTION
Generally, a plurality of integrated circuit chips are formed on a semiconductor substrate (wafer) by performing semiconductor thin film processes having peculiar properties. Following formation of the integrated circuit chips, the wafer is sawed for individualizing them. Thus, a vacant space exists between integrated circuit chips. Namely, a vacant space for sawing the wafer is formed between the integrated circuit chips. The vacant space is called a scribe line area. Elements constituting an integrated circuit chip are not formed at the scribe line area.
To assess electric properties of elements constituting an integrated circuit chip, a predetermined pattern of measuring elements or test elements (so-called test element group (TEG)) is formed on a scribe line area of a semiconductor wafer. The TEG is electrically tested for determining whether elements are suitably formed in integrated circuit chips formed on the wafer. A semiconductor device including measuring elements or test elements used for testing electric properties is disclosed in U.S. Pat. No. 6,177,733 entitled “SEMICONDUCTOR DEVICE”, U.S. Pat. No. 5,949,090 entitled “MOS TEG STRUCTURE”, and U.S. Pat. No. 5,654,582 entitled “CIRCUIT WAFER AND TEG AND ELECTRODE”.
Since the TEG is formed using the same process as a process for forming elements in integrated circuit chips, testing electric properties of the TEG is identical to testing electric properties of the elements formed in the integrated circuit chips. Accordingly, the properties of the integrated circuit chips can be correctly deduced by testing the TEG. Once the properties have been tested, there remains no reason to retain the TEG. So the TEG can be formed in a sacrificial area of the wafer. Hence, the TEG is disposed in a scribe line area of the wafer to prevent a decrease in the number of integrated circuit chips that otherwise could be produced from the wafer.
As shown in
FIG. 1
, a scribe line area
2
surrounds an integrated circuit chip area
3
where input pads, output pads, and MOS elements (not shown) are formed. A test element group (TEG) is disposed on the scribe line area. The TEG includes TEG modules each having a plurality of MOS elements.
The elements constituting the respective TEG modules are classified into, for example, a P-channel transistor for logic gate, an N-channel transistor for logic gate, a field N-channel transistor, a field P-channel transistor, a capacitor for logic gate, a contact chain, and a resistor. N-channel transistors for logic gate are disposed at one TEG module, while P-channel transistors for logic gate are disposed at another TEG module.
Referring to
FIG. 2
, each of TEG modules
10
a
,
10
b
, . . . , and
10
c
includes test elements (TE_
0
a
)-(TE_na), (TE_
0
b
)-(TE_nb), . . . and (TE_
0
c
)-(TE_nc) each being formed in a corresponding P-well area (or N-well area). For brevity of the description, one of TEG modules (e.g.,
10
a
) is described. It will be understood to a person skilled in the art that the other TEG modules are disposed by the same manner.
Each of the test elements (TE_
0
a
)-(TE_na) constituting the TEG module
10
a
is a MOS transistor having, for example, a source, a drain, a gate, and a body. A common source line
12
a
, a common gate line
14
a
, and a common body line
16
a
are extended on a well area of the TEG module in the same direction. Sources of the test elements are commonly connected to a common source pad area
18
a
through the common source line
12
a
. Gates of the test elements are commonly connected to a common gate pad
20
a
through the common gate line
14
a
. Bodies of the test elements are commonly connected to a common body pad
22
a
through the common body line
16
a
. The common source pad
18
a
, the common gate pad
20
a
, and the common body pad
22
a
are disposed at one side (e.g., right area) of an area of the TEG module
10
a
. Since the common body pad
22
a
formed in the TEG module
10
a
is electrically connected to the other modules
10
b
-
10
c
through a P-well, different voltages cannot be applied to the modules
10
a
-
10
c
. The common body pad
22
a
just has a structure to offer a measuring convenience.
Drains of the test elements (TE_
0
a
)-(TE_na) formed in the TEG module
10
a
are coupled to corresponding drain pads (
24
_
0
a
)-(
24
13
na), respectively. The drain pads (
24
_
0
a
)-(
24
_na) are disposed to be adjacent to corresponding test elements (TE
13
0
a
)-(TE_na). Unlike a common gate and source pads, drain pads are separately formed for measuring a drain current of the test elements (TE_
0
a
)-(TE_na) without an affect of the other test elements. That is, each of the test elements requires an independent drain pad (namely, a 1:1 ratio) so as to measure electric properties of the test elements formed in the TEG module
10
a
. If a drain pad is commonly used, a leakage current may flow through unselected test elements irrespective of any selected test element.
A trend in the area of integrated circuit design has been to reduce element size, recently from 0.19 micrometer to 0.10 micrometer or less. Similarly, there is a trend towards decreasing the width of a scribe line area, not a chip area. In view of the trends, the number of drain pads formed in respective TEG modules becomes a significant factor limiting the number of test elements available for use in the TEG module. This will now be explained in further detail below.
Referring to
FIG. 3
, there is illustrated a relationship between sizes of a drain pad and a test element. A size of a drain pad
24
_
0
a
is about 100×100 micrometers, while that of a test element TE_
0
a
is about 1×10 micrometers. As compared to an area occupied by the test element TE_
0
a
, an area occupied by the drain pad
24
13
0
a
is considerably larger. Therefore, as a width of a scribe line area becomes smaller, the number of test elements is limited due to the area occupied by the drain pads.
SUMMARY OF THE INVENTION
The above problem associated with the Background Art is addressed by the present invention as will be understood by reading and studying the following specification. An embodiment of the invention is directed to a test element group structure that lessens an extent to which the number of test transistors decreases in proportion to a reduction in scribe line area.
According to an aspect of the invention, a semiconductor wafer comprises a plurality of chip areas having circuit elements, a scribe line area for defining the chip areas, a test element group that is formed on the scribe line area and includes a plurality of test element group modules. Each of the test element group modules (TEG) has a source, a drain, a gate, and a body. Each of the TEG modules includes test transistors formed in substantially the same manner as the circuit elements, a first pad commonly connected to sources of the test transistors, and a second pad commonly connected to bodies of the test transistors. A third pad is commonly connected to gates of test transistors in the TEG modules. A plurality of fourth pads are connected to drains of respective test transistors of one TEG module, and are shared by respective test transistors of the other TEG modules. When corresponding test voltages are respectively applied to the first to fourth pads coupled to a test transistor in one selected from the TEG modules, substantially the same test voltage applied to the fourth pad is substantially simultaneously also applied to first and second pads of each of unselected TEG modules.
According to another aspect of the invention, a test element group is provided which is disposed in a scribe line area defined by chip areas formed on a semiconductor wafer. The test element group includes at least two test element group (TEG) modules each being form

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