Test device, test method and computer readable media

Details Test device, test method and computer readable media Test device, test method and computer readable media

2011-03-15

2011-03-15

Charioui, Mohamed (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

C702S079000, C702S072000, C714S700000

Reexamination Certificate

active

07908110

ABSTRACT:
Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by comparing the output signal to an expected value.

REFERENCES:
patent: 7099424 (2006-08-01), Chang et al.
patent: 2004/0122620 (2004-06-01), Doi et al.
patent: 2005/0111602 (2005-05-01), Suda et al.
patent: 2005/0193298 (2005-09-01), Inaba et al.
patent: 2005/0249001 (2005-11-01), Tanaka et al.
patent: 06-148279 (1994-05-01), None
patent: 08-122409 (1996-05-01), None
D.C.Keezer, D.Minier, M.Paradis, F.Binette , “Modular Extension of ATE to 5 Gbps,” USA, 2004, International Test Conference 2004 (ITC2004), p. 748-757 (Paper 26.3).

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