Test device for semiconductor memory device

Details Test device for semiconductor memory device Test device for semiconductor memory device

1993-03-08

1995-02-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365226, 371 211, G11C 2900

Patent

active

053880773

ABSTRACT:
There is shortened a test time to ensure data holding power supply voltage. A power supply voltage reduction circuit 3 is provided which reduces power supply voltage Vcc supplied to a power source supply terminal to a predetermined level. Further, a test mode judgement circuit 4 is provided which judges an undergoing test mode to be a data holding power supply voltage test mode and issues an active level test mode signal TM. A switching circuit 5 is further provided which is operable with an output from the power supply voltage reduction circuit 3 as power supply voltage when the test mode signal TM is at an active level to restrict an output data level of said data input buffer circuit 2 and supplies restricted voltage to a memory cell 1 while being operable with the power supply voltage Vcc on the power source supply terminal intactly as the power supply voltage when said signal TM is at an inactive level to supply the output data of the data input buffer circuit 2 to the memeory cell 1.

REFERENCES:
patent: 5079744 (1992-01-01), Tobita et al.
patent: 5159571 (1992-10-01), Ito et al.

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