Test device for a combinatorial logic circuit and integrated cir

Details Test device for a combinatorial logic circuit and integrated cir Test device for a combinatorial logic circuit and integrated cir

1987-01-08

1988-12-06

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

324158R, 371 15, 371 16, G01R 3128

Patent

active

047898216

ABSTRACT:
This device and method for testing a combinative logic circuit (4), includes on the one hand a circuit generating test sequences (30) for applying test logic signals to N inputs of the combinative logic circuit and, on the other hand, an output circuit (5) to analyze the output signals of the combinative logic circuit. These test sequences are successively applied to each of the N inputs (E1, E2, E3 and E4) so that an alternating series, at least twice, of logic "1"'s and of logic "0"'s while a word of N-1 bits is applied to the other inputs to ensure the transmission of the said alternating series to the output of the combinative logic circuit.

REFERENCES:
patent: T930005 (1975-01-01), Chia et al.
patent: 3924181 (1978-12-01), Alderson
patent: 4584683 (1986-04-01), Shimizu
Frohwerk; "Signature Analysis: A New Digital Field Service Method"; Hewlett Packard Journal; May 1977; vol. 28, No. 9 pp. 1-8.
Fasang; "Circuit Module Implements Practical Self Testing"; Electronics; May 19, 1982; pp. 164-165.
Konemann et al.; "Built In Test For Complex Digital Integrated Circuits"; 1980 IEEE Journal of Solid State Circuits, vol. 15, No. 3; Jun. 1980; pp. 315-319.
Baschiera et al.; "Test Generation For Cmos S-Open and S-On Faults"; Rapport De Reserche N.533; May 1985; pp. 1-49.

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