Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2000-11-17
2002-12-03
Le, N. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
Reexamination Certificate
active
06489783
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a test method or architecture, and more particularly to one for testing a dielectric layer.
BACKGROUND OF THE INVENTION
Up to the present, the test method for testing chips in the manufacturing process mainly is categorized into two types. One is to arrange the circuit lines in the test circuit beforehand after accomplishing the manufacturing procedure for package. It can test the inner of the chips through the specific pins after they are packaged. However, this test method is inefficient because it only performs the testing action after accomplishing the chip packaging. If there are some errors occurring in the manufacturing process or are some bugs present in the chip design to cause the chip incapable of anticipatively performing, the cost for performing the packaging procedure after accomplishing the manufacturing process will be wasted.
Another is to perform the test during the chips manufacturing process, which generally is called Wafer Accept Test (WAT). One generally accepted method for testing the dielectric layer is named Time Dependent Dielectric Breakdown (TDDB). The mechanism of TDDB is to form a test key of a dielectric layer in a wafer, and then an equivalent circuit of the test key can be treated as a capacitor. We can test the capacitors to estimate the characteristic and the lifetime of the dielectric layers of the chips being made of the same wafer. The implementing procedure is as follows:
Step 1: Setting a voltage value Vs in a Source Measurement Unit (SMU);
Step 2: Probing a test structure (having thereon the capacitors), applying thereto the voltage of Vs until there is a breakdown in either one of the capacitors, and recording a Time to Failure (TTF);
Step 3: Probing the next test structure and continuing the testing procedure until the amount of testing samples is enough to proceed the next Step 4, or else to go back to Step 2;
Step 4: Providing a deviation voltage DV smaller than the voltage of Vs, i.e. DV=Vs−&Dgr;V, and executing the involved method from Step 2;
Step 5: Processing the next Step 6 if the amounts of testing samples under the conditions of three different voltage values are enough, otherwise going back to Step 2; and
Step 6: Calculating the lifetime and the voltage acceleration factor &bgr; of the test structure according to the above collected data.
Although the above-mentioned test procedure can earlier obtain the result through testing the chip and cost less development cost, such method still has the defects as follows:
1. It costs more testing time, particularly needing to test multiple test structures for obtaining enough amount of testing samples if there is only one capacitor in each one of multiple test structures.
2. When there are multiple capacitors in the test structure, a SMU merely adopts a voltage value and tests a capacitor using this voltage value at a time. At the same time, the SMU can't execute any other things.
Moreover, there still are some misgivings about the possible pollution and oxidization in the unpackaged surface of the wafer if the test time for testing the dielectric layer is excessively prolonged.
Therefore, it will be important how to improve the test device for testing a dielectric layer to provide a plurality of voltages for a SMU to test a plurality of capacitors at the same time, and to have the less test time.
It is therefore tried by the applicant to deal with the above situation encountered by the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method and architecture for testing a dielectric layer in the chip manufacturing process.
It is further an object of the present invention to provide a method and architecture for testing a dielectric layer, in which there is provided a single power source having a plurality of voltage value for testing a plurality of capacitors at the same time.
It is still an object of the present invention to provide a test method and architecture for testing a dielectric layer, in which the test time is reduced and the test efficiency is increased.
It is additional an object of the present invention to provide an architecture for testing a dielectric layer having an extensible and flexible framework in accordance with different test demands and purposes.
According to the present invention, a test device adapted to be electrically connected between a power supply and a current detector for testing a dielectric layer including a first capacitor and a second capacitor. The device includes a first current-limiting apparatus electrically connected to the first capacitor in series, a second current-limiting apparatus electrically connected to the second capacitor in series, and a voltage-regulating apparatus electrically connected to the second capacitor and the second current-limiting apparatus in series.
Certainly, the first current-limiting apparatus and the first capacitor electrically can be connected to the second current-limiting apparatus and the second capacitor.
Certainly, the current detector can probe an occurring current to determine a breakdown of the dielectric layer.
Preferably the breakdown is defined as a breakdown current of either one of the first capacitor and the second capacitor so that the breakdown current will flow through the one capacitor.
Preferably the breakdown current for the first capacitor has a first value, the breakdown current for the second capacitor has a second value, and the second value is different from the first value.
Certainly, the first current-limiting apparatus and the second current-limiting apparatus can be resistors.
Certainly, the voltage-regulating apparatus can be a diode.
Preferably the dielectric layer is formed in a process of making a chip.
According to a further aspect of the present invention, a test device adapted to be electrically connected between a power supply and a current detector for testing a dielectric layer including a plurality of capacitors. The device includes a plurality of current-limiting apparatuses electrically connected to the plurality of capacitors in series respectively, and at least a voltage-regulating apparatus electrically connected to the pluralities of current-limiting apparatuses and the capacitors in series.
Preferably the current detector probes an occurring current to determine a breakdown of the dielectric layer.
Preferably the breakdown is defined as a breakdown current of one of the plurality of capacitors so that the breakdown current will flow through the one capacitor.
Certainly, the occurring current values for the plurality of capacitors can be different from one another.
According to a yet aspect of the present invention, a test method includes steps of providing a test device for testing a dielectric layer including at least a first capacitor and a second capacitor, providing a voltage into the test device, and probing an occurring current to determine a breakdown current from either one of the first capacitor and the second capacitor.
Certainly, the method can further include providing a first current-limiting apparatus electrically connected to the first capacitor in series; providing a second current-limiting apparatus electrically connected to the second capacitor in series, and providing a voltage-regulating apparatus electrically connected to the second current-limited apparatus and the second capacitance in series.
Preferable the breakdown current for the first capacitor has a first value, the breakdown current for the second capacitor has a second value, and the second value is different from the first value
The present invention may best be understood through the following descriptions with reference to the accompanying drawings, in which:
REFERENCES:
patent: 4683417 (1987-07-01), De Burgat et al.
patent: 4906939 (1990-03-01), Berrigan et al.
patent: 5936409 (1999-08-01), Nishioka
patent: 6094788 (2000-08-01), Farahmandi et al.
Lay Ming-Yi
Liu Jian-Yu
Dann Dorfman Herrell and Skillman
Le N.
LeRoux Etienne P
Skillman Henry H.
Winbond Electronics Corp.
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