Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-12-05
2004-07-13
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06762611
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a probe card configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory components located on a wafer, in parallel. The probe card configuration has a carrier board for bringing up electric signal lines from a test system and has contact-making needles for producing electrical connections with contact areas on the circuits to be tested.
Current DRAM (Dynamic Random Access Memory) chips are tested with expensive memory test systems. Test programs for checking the functional suitability of the memory chips are used on these testers. In this case, signals with exactly defined voltage levels are applied to the semiconductor circuits to be tested at exactly defined times. During the checking of the read function of the DUT (Device Under Test), it is also possible to read signals coming into the test instrument from the DUT at precisely defined times and to compare them with expected signal values.
Because of the high frequencies at which current memory modules operate, for example 200 to 300 MHz in the case of DDR (Double Data Rate) DRAMs and 400 to 800 MHz in the case of Rambus DRAMs, the these chips specify highly accurate signals. For example, in the case of DDR memories, signal specifications of the order of magnitude of 500 ps are common. The production or memory test systems that are used therefore have to meet extremely high technical requirements, which leads to correspondingly high production and testing costs. At present, DRAM test instruments that meet the aforementioned conditions cost several millions of dollars each. All of this causes the testing costs to be up to 30% of the production costs in the case of the highest frequency memory modules.
Functional testing of the memory modules is carried out both at the wafer level, and following separation, at the module level. Nowadays, at the wafer level, the basic function of the memory chip is usually checked in relatively low frequency range of about 10 to 100 MHz. The higher-frequency tests are then carried out following mounting in the encapsulated state, on specific module testers.
In principle, it would be desirable to carry out a high-speed test on the memory components as early as at the wafer level, since then the functional test is carried out at a time which is beneficial from the value creation point of view, so that there is a great potential for cost savings.
However, high-frequency tests at the wafer level are possible only to a limited extent at present, which is mainly attributable to the large geometric dimensions of the test configuration. From the pin electronics of the tester as far as the components to be tested via the test head, the probe card configuration has to bridge dimensions in the order of magnitude of 10 cm to 1 m. This is virtually impossible with adequate accuracy and with high parallelism at frequencies of 200 MHz to 1 GHz.
U.S. Pat. No. 6,064,213 discloses a probe card configuration. Published German Patent application DE 198 26 314 A1 discloses an arrangement for testing a plurality of integrated circuits in parallel. The arrangement has a carrier board to bring up electrical signal lines of a test system and has a plurality of mounts to accommodate the integrated circuits to be tested. This is where the invention begins.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a probe card configuration for testing a plurality of integrated circuits on a wafer in parallel and a method of using the probe card configuration to test the plurality of the integrated circuits on the wafer which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a probe card configuration for testing a plurality of integrated circuits in parallel using a test system. The probe card configuration includes a carrier board for receiving electrical signal lines of the test system. The carrier board defines a plane. The probe card configuration includes contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested. The contact-making needles are for connecting to the electrical signal lines of the test system to produce signal paths between the test system and the integrated circuits to be tested. The probe card configuration also includes a plurality of active modules configured on the carrier board. Each one of the plurality of the active modules is assigned to one of the integrated circuits to be tested in parallel. Each one of the plurality of the active modules is inserted into ones of the signal paths that are between the test system and the assigned one of the integrated circuits to be tested. The plurality of the active modules are configured at least partly overlapping in a direction at right angles to the plane of the carrier board.
In accordance with an added feature of the invention, each one of the plurality of the integrated circuits has a longest extent; each one of the plurality of the active modules has a longest extent; and the longest extent of each one of the plurality of the active modules is greater than the longest extent of the assigned one of the integrated circuits to be tested.
With the foregoing and other objects in view there is provided, in accordance with the invention, a probe card configuration for testing a plurality of integrated circuits in parallel using a test system. The probe card configuration includes a carrier board for receiving electrical signal lines of the test system. The carrier board defines a plane. The probe card configuration includes contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested. The contact-making needles are for connection with the electrical signal lines of the test system to produce signal paths between the test system and the integrated circuits to be tested. The probe card configuration also includes a plurality of active modules configured on the carrier board. Each one of the plurality of the active modules is assigned to one of the integrated circuits to be tested in parallel. Each one of the plurality of the active modules is inserted into ones of the signal paths that are between the test system and the respective assigned one of the integrated circuits to be tested. Each one of the plurality of the active modules has a longest extent. The longest extent of each one of the plurality of the active modules is configured non-parallel with the plane of the carrier board.
In accordance with an additional feature of the invention, the longest extent of each one of the plurality of the active modules is configured at right angles with respect to the plane of the carrier board.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the testing a plurality of integrated circuits on a wafer in parallel, which includes steps of: providing the probe card configuration according to one of the above described embodiments; making contact between a first group of the integrated circuits to be tested on the wafer and the contact-making needles; performing a test routine with the first group of the integrated circuits to be tested; making contact between a second group of the integrated circuits to be tested on the wafer and the contact-making needles, the second group of the integrated circuits being located disjunct with respect to the first group of the integrated circuits; performing a test routine with the second group of the integrated circuits to be tested; configuring the integrated circuits to be tested on the wafer in a regular rectangular grid form having main directions at right angles to one another; configuring the first group of the integrated circuits and the second group of the integrated circuits to extend along the main directions of the grid; performing the step of ma
Hübner Michael
Krause Gunnar
Kuhn Justus
Müller Jochen
Pöchmüller Peter
Greenberg Laurence A.
Infineon Techologies AG
Karlsen Ernest
Locher Ralph E.
Stemer Werner H.
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