Test circuit of semiconductor memory device

Details Test circuit of semiconductor memory device Test circuit of semiconductor memory device

1991-07-22

1993-07-13

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 371 212, G11C 2900

Patent

active

052280004

ABSTRACT:
In a test mode, bit information of the same logic is written into a corresponding memory cell of each of subarray 5a-5d. Bit information written in respective memory cells is simultaneously read and supplied to exclusive-OR gates 12a-12d. Each of exclusive-OR gates logics of read bit information and an expected value data supplied as an input to an external input pin D.sub.IN to supply the test determination result as an output. The outputs of respective exclusive-OR gates 12a-12d are serially supplied, through transistors 18a-18d which are sequentially and selectively turned on by a shift register 15, to an external output pin D.sub.OUT.

REFERENCES:
patent: 4672582 (1987-06-01), Nishimura et al.
patent: 4692901 (1987-09-01), Kumanoya et al.
patent: 4860259 (1989-08-01), Tobita
patent: 4873669 (1989-10-01), Furutani et al.
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4962500 (1990-10-01), Nakagawa
patent: 5016220 (1991-05-01), Yamagata
patent: 5060198 (1991-10-01), Kowalski
IEEE International Solid-State Circuits Conference, "FAM 17.2: A 90ns 1Mb DRAM with Multi-Bit Test Mode", Kumanoya, et al., Feb. 15, 1985, pp. 240-241 and pp. 352-353.
IEEE International Solid-State Circuits conference, "WAM 1.1: A 90ns 4Mb DRAM in a 300 mil DIP", Feb. 25, 1987, Mashiko et al., pp. 12-13, 314-315.

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