Test circuit inserting method and apparatus for a...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C716S030000, C714S030000, C714S726000

Reexamination Certificate

active

10976323

ABSTRACT:
A method to reduce the load of layout design and attain a high fault coverage while preventing increase in chip size in test point insertion for a semiconductor integrated circuit. Initial layout is performed on the basis of the circuit information. Interconnection pairs are extracted from a layout result. Test point insertion candidates are extracted on the basis of the controllability probabilities and the interconnection pairs. If test point insertion candidates exist, test point insertion positions are selected. Circuit structures of test points to be inserted there are selected. Test points having those circuit structures are inserted virtually. Whether the circuit overhead of a layout result is within a prescribed range is judged. If the circuit overhead exceeds the prescribed range, the number of test points is reduced.

REFERENCES:
patent: 5450414 (1995-09-01), Lin
patent: 5737340 (1998-04-01), Tamarapalli et al.
patent: 6038691 (2000-03-01), Nakao et al.
patent: 6059451 (2000-05-01), Scott et al.
patent: 6070261 (2000-05-01), Tamarapalli et al.
patent: 6301688 (2001-10-01), Roy
patent: 6782515 (2004-08-01), Scott et al.
patent: 6922803 (2005-07-01), Nakao et al.
patent: 7036060 (2006-04-01), Nakao et al.
patent: 2002/0073373 (2002-06-01), Nakao et al.
patent: 2003/0154432 (2003-08-01), Scott et al.
patent: 2003/0200492 (2003-10-01), Nakao et al.
patent: 2000-250946 (2000-09-01), None

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