Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-17
2007-04-17
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C714S030000, C714S726000
Reexamination Certificate
active
10976323
ABSTRACT:
A method to reduce the load of layout design and attain a high fault coverage while preventing increase in chip size in test point insertion for a semiconductor integrated circuit. Initial layout is performed on the basis of the circuit information. Interconnection pairs are extracted from a layout result. Test point insertion candidates are extracted on the basis of the controllability probabilities and the interconnection pairs. If test point insertion candidates exist, test point insertion positions are selected. Circuit structures of test points to be inserted there are selected. Test points having those circuit structures are inserted virtually. Whether the circuit overhead of a layout result is within a prescribed range is judged. If the circuit overhead exceeds the prescribed range, the number of test points is reduced.
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Kik Phallaka
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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