Test circuit in clock synchronous semiconductor memory device

Details Test circuit in clock synchronous semiconductor memory device Test circuit in clock synchronous semiconductor memory device

1994-05-19

1996-04-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365233, G11C 700

Patent

active

055110290

ABSTRACT:
In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

REFERENCES:
patent: 4424581 (1984-01-01), Kawai
patent: 5311519 (1994-05-01), Getzlaff
patent: 5313424 (1994-05-01), Adams
patent: 5355342 (1994-10-01), Veoka
patent: 5367488 (1994-11-01), An

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