Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-08-17
2001-07-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S189020, C365S189090
Reexamination Certificate
active
06256243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a monolithically integrated test circuit for testing a digital semiconductor circuit configuration having a large number of elements to be tested. The test circuit is formed on the same semiconductor chip as the circuit configuration under test. The test circuit includes a read and write circuit for writing and reading a test data pattern to and from the elements to be tested, a comparison circuit, and a pattern variation circuit which can be activated by an activation signal.
When testing the operation of a semiconductor memory, as a particularly preferred embodiment of the semiconductor circuit configuration according to the invention, apart from the individual data and address lines, the memory cells are, in particular, checked with regard to manufacturing faults. Since large numbers of cells have to be tested when the semiconductor memories are still part of the wafer, they are generally addressed combined into groups, rather than individually. In such a compression test, the data bits are normally combined into groups and are connected to a smaller number of I/O interfaces (I/O=in-out) than the chip actually has. Depending on the chip architecture, one data bit is in each case written to a number of data lines when a write access is made via the small number of I/O interfaces. When a read access is made, the data bits of these data lines are checked in groups to ensure that they are equal, and the result of this test is output respectively as PASS or FAIL information to the small number of I/O interfaces. One disadvantage of this procedure is that it is impossible to write any desired number of data patterns to the memory, since the data lines that are combined all have a fixed polarity. Since the physical environment of the memory cells is different and can cause polarity-dependent failures, some defective memory cells are overlooked in such a “rigid” test. Such a test is thus useless, since even a single memory cell defect can lead to the entire component being scrapped. A further disadvantage of this procedure is that testing for equality in the situation where all the combined data bits are “wrong” can lead to a supposedly “correct” result.
U.S. Pat. No. 5,418,790 discloses a test circuit for detecting interference for a semiconductor memory apparatus which, for simultaneous investigation of memory cells, programs the memory cells simultaneously with a single test bit that is common to all the memory cells, and combines the determined data values stored on the basis of the test bit such that a check is carried out at the same time to confirm that all the data values are absolutely identical. Furthermore, the previously known apparatus has logic apparatuses which can be activated by a signal, and by which the test bit and the data values determined from the memory cells can be inverted simultaneously before they are combined. However, the previously known apparatus has the disadvantages mentioned above.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test circuit for testing a digital semiconductor circuit configuration that overcomes the disadvantages of the prior art devices and methods of this general type, in which a reduced number of addresses and/or IO interfaces at a wafer and chip level are required, which is physically simple, and in which the test accuracy is at the same time improved.
With the foregoing and other objects in view there is provided, in accordance with the invention, a combination of a digital semiconductor circuit configuration formed on a semiconductor chip and having a large number of elements to be tested, and a monolithically integrated test circuit for testing the elements to be tested and formed on the semiconductor chip. The test circuit includes a read and write circuit for writing and reading a test data pattern having a given width to and from the elements to be tested and a test data pattern register for temporarily storing the test data pattern. A pattern variation circuit is provided which receives and is activated by an activation signal. The pattern variation circuit is connected to the test data pattern register and to the read and write circuit. The pattern variation circuit varies the test data pattern received from the test data pattern register before writing it into the elements to be tested. A comparison circuit is connected to the read and write circuit and to the pattern variation circuit. The comparison circuit tests for a difference between written data and read data of the elements to be tested.
The invention provides that a test data pattern register is provided for temporary storage of the test data patterns, and that the pattern variation circuit which can be activated by the activation signal varies the test data pattern from the test data pattern register before writing into the elements to be tested. The comparison circuit is configured in such a way that it tests for a difference between the written and read data of the elements to be tested.
In one particularly preferred embodiment of the invention, the activation signal for activating the pattern variation circuit is supplied via a pad, which is already present on the semiconductor chip, and is connected to the pattern variation circuit. The advantage of this configuration is that the semiconductor circuit configuration can be tested with varying patterns while still part of the wafer, without the test data pattern register having to be reloaded. To do this, it is advantageous for the digital semiconductor circuit configuration to be operable in two modes. The first mode is a normal mode in which the test circuit is deactivated and the semiconductor circuit configuration has the I/O lines associated with it. The second mode is a test mode in which the pad, which is already present on the semiconductor chip, is connected to the pattern variation circuit of the test circuit. The pad is preferably decoupled from the pattern variation circuit in the normal mode and in the normal mode is intended for coupling the digital semiconductor circuit configuration to a signal.
In another preferred embodiment of the invention, the comparison circuit of the test circuit is formed with a number of logic gates corresponding to the width of the test data pattern, which gates compare the data read from and to be written to the semiconductor memory bit-by-bit. Based on this development, the test circuit is advantageously equipped with an addition gate, which is coupled to the logic gates of the comparison circuit. The addition gate, which is advantageously formed by a NOR gate, combines the results of the logic gates of the comparison circuit to form a test result. In this case, a logic “zero” as the result from the NOR gate is then used as a FAIL signal, and a logic “one” is then used as a PASS signal.
In a further preferred embodiment of the invention, the pattern variation circuit is formed by a number of logic gates corresponding to the width of the test data pattern, which gates vary the test data pattern of the test data pattern register bit-by-bit. To do this, the pattern variation circuit can advantageously be activated by an activation signal. The logic gates in the comparison circuit and in the pattern variation circuit are advantageously formed by exclusive-OR gates.
In another preferred embodiment of the invention, the test circuit has a result variation circuit, which contains a number of logic gates corresponding to the width of the test data pattern. The logic gates are connected to the outputs of the logic gates in the comparison circuit and are disposed downstream from which the addition gate is connected to the outputs. The logic gates in the result variation circuit are in this case preferably formed by exclusive-OR gates, which are activated jointly by a result variation signal.
When a read access is made, the data bits in each group are linked to the varied test data pattern bits in such a way that the previous operation is reversed. If
Bröke Jan Ten
Kund Michael
Nikutta Wolfgang
Savignac Dominique
Greenberg Laurence A.
Infineon - Technologies AG
Lam David
Lerner Herbert L.
Nelms David
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