Test circuit for refresh counter of clock synchronous type semic

Details Test circuit for refresh counter of clock synchronous type semic Test circuit for refresh counter of clock synchronous type semic

1994-05-19

1995-11-28

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, G11C 1134

Patent

active

054714303

ABSTRACT:
A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

REFERENCES:
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 5021951 (1991-06-01), Baba
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5299168 (1994-03-01), Kang
patent: 5321661 (1994-06-01), Iwakiri et al.

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