Test circuit for non-volatile storage cell

Details Test circuit for non-volatile storage cell Test circuit for non-volatile storage cell

1989-09-29

1991-07-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365185, 371 211, G11C 700, G11C 2900

Patent

active

050311522

ABSTRACT:
A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.

REFERENCES:
patent: 4803659 (1989-02-01), Hallenbeck
patent: 4862418 (1988-08-01), Cuppens et al.

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