Test circuit for memory

Details Test circuit for memory Test circuit for memory

2007-09-25

2007-09-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S702000

Reexamination Certificate

active

10646868

ABSTRACT:
Each signal generating circuit for generating a CS signal, an address signal, a data signal or an R/W signal of a memory to be tested, and a test setting control circuit for generating a control data of these signal generating circuits are provided. The signal generating circuits and the test setting control circuit have shift registers, and a control data and a test data are serially input to these shift registers from external terminals.

REFERENCES:
patent: 4446514 (1984-05-01), Brown et al.
patent: 4821238 (1989-04-01), Tatematsu
patent: 5668815 (1997-09-01), Gittinger et al.
patent: 5883844 (1999-03-01), So
patent: 5987635 (1999-11-01), Kishi et al.
patent: 6034907 (2000-03-01), Haraguchi
patent: 6473873 (2002-10-01), Akamatsu et al.
patent: 2001/0056557 (2001-12-01), Kawagoe et al.
patent: 2002/0049940 (2002-04-01), Giaume et al.
patent: 2002/0093862 (2002-07-01), Akioka
patent: 2003/0120974 (2003-06-01), Adams et al.
patent: 02216565 (1990-08-01), None
patent: 2001-297598 (2001-10-01), None
patent: 2002/042493 (2002-02-01), None
patent: 2002100200 (2002-04-01), None
Patent Abstracts of Japan, vol. 2002, No. 02, Apr. 2, 2002, Abstract only.

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