Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-12-22
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S238500, C365S185330
Reexamination Certificate
active
06188621
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a test circuit for a flash memory device and method thereof. In particular, the present invention relates to a test circuit for a flash memory device and method thereof, which allow circuits therein to be designed in consideration of the test process during the design process of a flash memory device so that the test mode of the flash memory device can be automatically repeated without manipulation and command by the operator when a specific voltage is applied to its external pins, thereby reducing the costs and time necessary to test it.
DESCRIPTION OF THE PRIOR ART
In designing an electronic circuit, the problem of reliability test on a device becomes an integral part. This is because unexpected variables such as temperature, external voltage etc. become increased due to higher integration and ultra micro-miniature process of the device and it also becomes important to manufacture reliable products in a short development period in designing an electronic circuit. Thus, the circuit design to facilitate the test must be considered at the early stage of developing the products, which is important not inferior to designing the products.
The test process for securing reliability of the flash memory commonly proceeds as follows. First, it checks whether programming into the entire sectors except for the protected sector in the chip is successfully accomplished or not. In order to accomplish this, it performs a byte program into the entire addresses for the entire sectors that are not protected. If this process is completed, it checks whether there is any fail in the chip by performing erase process. At this time, the erase process for the entire sectors must be performed for the entire sectors that are not protected, as in the programming. As above, via repeated programming and erase process, if it can be secured that no fail are found therein, reliability of the chip can be secured. During this process, the extracted fail chips are repaired or discarded.
In a conventional method, it checks the fail by performing a programming on individual sectors and erasing it again. Thus, there is a problem in that it requires a lot of costs and time to complete the test on the entire sectors. Also, there will be the case, to an extreme, in which the cost required to test a lot of chips is comparable to that required to design the products, which cause to lower the efficiency of the test process.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems involved in the prior art, and to provide a test circuit and method thereof by which the program and erase process can be automatically connected by designing the circuit in consideration of test during the design process of a product and the test mode can be also finished depending on the fail flag when any fail is found within a chip during a specific cycle, thus reducing the entire period necessary to develop the product and the costs and time necessary to test it.
To achieve the above object, a test circuit for a flash memory device according to the present invention is characterized in that it comprises a byte program means for performing a byte program according to a byte program enable signal and a cell address signal and outputting the last address signal of a sector, a program fail signal and an address signal of the fail cell; a chip erase means for performing a chip erase operation according to an erase enable signal and said sector address signal and for outputting an erase fail signal and an address signal of a fail sector; a sector address increment means for increasing a sector address according to said sector address signal and outputting the last sector address signal; a first means for generating a test signal according to the test enable signal, said last sector address signal, a test erase enable signal, said program fail signal and said erase fail signal; a second means for generating a test program enable signal or a test erase enable signal according to the last sector address signal and the test signal to supply them to said byte program means or said chip erase means; and an address/sector decoder for decoding the address from an address pad into a cell address and a sector address to supply them said byte program means and said chip erase means, respectively.
Also, a method of testing a flash memory device according to the present invention is characterized in that it comprises the steps of confirming whether the current sector has been protected or not as the test mode begins, if it has been protected, checking whether it is the last address of the sector or not, and if not performing a byte programming operation, if any fail occurs during the byte programming operation, finishing the test mode, and if it is not, checking whether the address in programming is the last address of the sector, and if it is not the last address of the sector, proceeding to the step to check whether the sector has been protected, and if it is the last address of the sector, confirming whether the sector in programming is the last sector address or not, if the sector in programming is not the last sector address, increasing the sector address and then proceeding to the step to check whether the sector has been protected or not, and if it is the last sector address, finishing the byte program; checking whether the sector for erase has been protected or not, and if it has been protected proceeding to the step to check whether the sector address in erase is the last sector address or not, and if it has not been protected performing a chip erase; if any fail occurs during the chip erase, finishing the test mode, and if not checking whether the sector address in erase is the last sector address or not; as a result of checking whether it is the last sector address or not, if it is not the last sector address, increasing the sector address and then proceeding to the step to check whether the sector for performing the chip erase has been protected or not; and as a result of checking whether it is the last sector address or not, if it is the last sector address, restarting the test mode.
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Hyundai Electroncis Industries Co., Ltd.
Le Thong
Nelms David
Pennie & Edmonds LLP
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