Test circuit for a semiconductor memory device and method for bu

Details Test circuit for a semiconductor memory device and method for bu Test circuit for a semiconductor memory device and method for bu

1998-10-21

2000-04-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365203, 36523004, G11C 700

Patent

active

060551992

ABSTRACT:
A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

REFERENCES:
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5357193 (1994-10-01), Tanaka et al.
patent: 5381373 (1995-01-01), Ohsawa
patent: 5590079 (1996-12-01), Lee et al.
patent: 5638331 (1997-06-01), Cha et al.
"Wafer Burn-in (WBI) Technology for RAM's", Tohru Furuyama, et al. International Electron Devices Meeting, Technical Digest, 1993, pp. 639-642.

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