Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-08-22
2003-11-18
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000
Reexamination Certificate
active
06650583
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test circuit device and a semiconductor integrated circuit device for testing a semiconductor memory device and more particularly, to a test circuit device and a semiconductor integrated circuit device for identifying an error in stored data at a memory cell level.
2. Description of the Background Art
In a memory cell of a DRAM (Dynamic Random Access Memory), data is held in a charge form in a capacitor. In the case of reading data from a memory cell which simply accumulate charges in a capacitor and therefore could not drive a signal line (bit line), with a pair of complementary data lines used as data lines for receiving memory cell data, a small potential difference between the complementary data lines of the pair is amplified to enable read out the memory cell data.
FIG. 33
is a diagram schematically showing the configuration of a main portion of a conventional DRAM. In
FIG. 33
, a pair of bit lines BL and ZBL and two word lines WL
0
and WL
1
are shown. A memory cell MC
0
is disposed at a crossing between bit line BL and word line WL
0
, and a memory cell MC
1
is disposed at a crossing between bit line ZBL and word line WL
1
.
Each of memory cells MC
0
and MC
1
includes a capacitor MQ for storing data and an access transistor MT for coupling a corresponding capacitor MQ to an associated bit line BL or ZBL in accordance with a signal potential on a corresponding word line WL (WL
0
or WL
1
). Access transistor MT is formed of an N-channel MOS transistor (insulated gate field effect transistor).
Corresponding to the pair of bit lines BL and ZBL, a sense amplifier SA is disposed. When activated, sense amplifier SA amplifies the potential difference between bit lines BL and ZBL to drive bit lines BL and ZBL to the H level (for example, power supply voltage level) and the L level (for example, ground voltage level) in accordance with data stored in a selected memory cell.
Bit lines BL and ZBL are coupled to internal data lines IO and ZIO via a column selection gate YG. Column selection gate YG includes transfer gates TX, which are made conductive in response to a column selection signal CSL to couple bit line BL to internal data line
10
, and complementary bit line ZBL to complementary internal data line ZIO. Connection between bit lines BL and ZBL and internal data lines IO and ZIO is uniquely determined irrespective of the position of a selected memory cell.
Internal data lines IO and ZIO are coupled to a write/read circuit RWK, which in turn is coupled to an input/output circuit IOK for inputting/outputting data externally.
In the configuration illustrated in
FIG. 33
, one word line is driven to a selected state, and data stored in a memory cell is read onto one of bit lines BL and ZBL. For example, when word line WL
0
is selected, the data stored in memory capacitor MQ of memory cell MC
0
is transmitted to bit line BL. Complementary bit line ZBL maintains a precharge state. Sense amplifier SA amplifies the potential difference between bit lines BL and ZBL. Consequently, even if a small potential change is caused on bit line BL in accordance with the charges stored in memory capacitor MQ, by amplifying the potential difference between bit lines BL and ZBL, the data in the memory cell can be read with reliability.
Where word line WL
1
is selected, the charges stored in capacitor MQ in memory cell MC
1
are transmitted to bit line ZBL, and bit line BL maintains the precharge voltage level.
Therefore, when a memory cell is selected, data stored in the memory cell is transmitted to one of bit lines BL and ZBL, and the other bit line maintains the precharge voltage level and is used as a reference bit line supplying a reference potential at the time of the differential amplification. By using complementary bit lines BL and ZBL, even if the data is stored in a charge form in capacitor MQ in memory cell MC (MC
0
or MC
1
), data can be accurately read.
Write/read circuit RWK includes a write circuit which is activated in writing data to generate complementary write data onto internal data lines IO and ZIO, and a preamplifier (read circuit) which is activated in reading data to amplify complementary internal data on internal data lines IO and ZIO and transmit the amplified data to input/output circuit IOK.
In writing data, input/output circuit IOK generates internal data in accordance with external data DQ and supplies the generated internal data to write/read circuit RWK. In reading data, input/output circuit IOK buffers internal read data supplied from write/read circuit RWK to generate external output data DQ.
In selecting a column, column selection gate YG couples bit lines BL and ZBL to internal data lines IO and ZIO, respectively, in accordance with a column selection signal CSL. The connection between bit lines BL and ZBL and internal data lines IO and ZIO is uniquely determined. There is consequently such a case that the logic level of external write data and that of data actually stored in a memory cell are different from each other depending on the position of the memory cell.
FIG. 34
is a diagram showing an example of data stored in a memory cell in writing data. It is now assumed that, as shown in
FIG. 34
, in writing data, write/read circuit RWK generates complementary data D and ZD in accordance with internal write data D from input/output circuit RWK and transmits complementary data D and ZD to internal data lines IO and ZIO, respectively, and internal write data D and ZD are at the H and L levels, respectively. When bit lines BL and ZBL are connected to internal data lines IO and ZIO, respectively, in response to column selection signal CSL, data D at the H level is transmitted to bit line BL, and complementary write data ZD on complementary internal data line ZIO is transmitted to complementary bit line ZBL.
Consequently, when word line WL
0
is selected, H-level data corresponding to external write data is written into and stored in memory cell MC
0
. On the other hand, when word line WL
1
is selected and memory cell MC
1
is selected, complementary write data ZD is written into and stored in memory cell MC
1
.
That is, data at the same logic level as that of external write data D is stored in the memory cell connected to bit line BL, while complementary write data ZD at the logic level opposite to that of external write data D is stored in the memory cell connected to complementary bit line ZBL.
FIG. 35
is a diagram showing read data in reading data stored in a memory cell. It is now assumed that, in
FIG. 35
, H-level data is stored in memory cell MC
0
and L-level data is stored in memory cell MC
1
.
When memory cell MC
0
is selected, H-level data is read onto bit line BL. A potential difference caused between bit lines BL and ZBL is amplified by sense amplifier SA, bit line BL is driven to, for example, the power supply voltage level, and bit line ZBL is driven to, for example, the ground voltage level. Internal read data RQ and ZRQ on bit lines BL and ZBL are at the H level and the L level, respectively.
When column selection gate YG is made conductive in response to column selection signal CSL, internal read data RQ on bit line BL is transmitted to internal data line IO, and internal read data ZRQ is transmitted to internal data line ZIO. In reading data, write/read circuit RWK generates internal read data RQ in accordance with data RQ and ZRQ on internal data lines IO and ZIO. That is, in reading data, write/read circuit RWK generates internal read data RQ at the same logic level as that of read data RQ on internal data line IO. When input/output circuit IOK generates external output data DQ in accordance with internal read data RQ transmitted from write/read circuit RWK, external output data DQ at the H level the same in level as the H-level data stored in memory cell MC
0
is generated.
On the other hand, when memory cell MC
1
is selected, the L-level data is transmitted to complementary bit line ZBL. Sense amplifier SA amplifies a potential differe
Dosaka Katsumi
Haraguchi Masaru
Mitsubishi Denki & Kabushiki Kaisha
Phung Anh
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