Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
2006-10-17
2006-10-17
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
Reexamination Certificate
active
07124334
ABSTRACT:
A communication system for transmitting and receiving data at high speed can be self-tested at actual operating speed with low cost, and without increasing the chip area. A test signal generation unit generates test parallel data. A transmitter for test purpose converts the parallel data into serial data. A selector selectively supplies the serial data output from the transmitter to a receiver during a test operation. The receiver converts the serial data into parallel data. After that, a detector detects an error in the parallel data output from the receiver. In this case, only the transmitter is disposed in correspondence with receivers. Serial data output from the transmitters is supplied to the receivers through the selector.
REFERENCES:
patent: 5477364 (1995-12-01), Pearson
patent: 5497377 (1996-03-01), Muto et al.
patent: 5896213 (1999-04-01), Nagahori et al.
patent: 6279139 (2001-08-01), Miyasita
patent: 6871311 (2005-03-01), Watanabe et al.
Kawasaki Microelectronics Inc.
Kerveros James C
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