Test circuit and method for refresh and descrambling in an integ

Details Test circuit and method for refresh and descrambling in an integ Test circuit and method for refresh and descrambling in an integ

1997-05-02

1998-12-01

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058449140

ABSTRACT:
A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

REFERENCES:
patent: 5737748 (1998-04-01), Shigeeda
patent: 5737764 (1998-04-01), Shigeeda

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