Test circuit and method for multilevel cell flash memory

Details Test circuit and method for multilevel cell flash memory Test circuit and method for multilevel cell flash memory

2007-12-10

2010-02-09

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S721000

Reexamination Certificate

active

07661041

ABSTRACT:
A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

REFERENCES:
patent: 5099143 (1992-03-01), Arakawa
patent: 5659550 (1997-08-01), Mehrotra et al.
patent: 6301157 (2001-10-01), Riva et al.
patent: 6532556 (2003-03-01), Wong et al.
patent: 6754107 (2004-06-01), Khouri et al.
patent: 6768685 (2004-07-01), Scheuerlein
patent: 7050328 (2006-05-01), Khouri et al.

Affiliated with

Also associated with

Rating

Test circuit and method for multilevel cell flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuit and method for multilevel cell flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit and method for multilevel cell flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4208796