Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-01-29
2008-01-29
Kerveros, James C. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
10991702
ABSTRACT:
A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
REFERENCES:
patent: 6532556 (2003-03-01), Wong et al.
patent: 6754107 (2004-06-01), Khouri et al.
patent: 7050328 (2006-05-01), Khouri et al.
Hoang Loc B.
Ly Anh
Nguyen Hung Q.
Nguyen Sang Thanh
Saiki William John
DLA Piper (US) LLP
Kerveros James C.
Silicon Storage Technology, Inc.
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