Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-13
2001-07-17
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090, C324S765010
Reexamination Certificate
active
06262581
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to an apparatus for testing an electrical device, and more particularly, to an apparatus for testing an unpackaged, or bare, microchip.
2. Description of the Related Art
A need for more compact electronic devices has accelerated development of multi-chip modules (MCM's) which contain multiple semiconductor chips in a single package. However, the successful introduction of multi-chip modules to a commercial market requires a technology for producing known good dies (KGD's), i.e., bare chips that are as reliable as packaged chips. Therefore, there is a need in the industry for technologies that can test bare chips, both physical and electrical reliability tests, such as burn-in tests and electrical performance tests, in a reliable and cost-effective manner.
Two types of bare chip testing methods are available. One is a wafer-level test, and the other is a die-level test. In general, the wafer-level test has several technical difficulties associated with it. For example, a probe card having probes at a sufficiently fine pitch is difficult to fabricate. A conventional probe card often causes contact failures due to a slight bending of the probes. Further, the trend in the industry is toward larger wafers, with more chips per wafer and a higher degree of integration of circuitry into the chips, which exacerbates the problem.
In contrast, the die-level test is performed after the wafer is sawn into individual dies, or chips. A typical die-level test employs a carrier to mount and carry a bare, or unpackaged, chip during testing. The chip undergoes all the same reliability and electrical tests as a packaged chip while contained in the test carrier. For example, the carrier containing the bare chip is inserted into a test socket for an electrical performance test of the chip. After all the tests are completed, the bare chips are unloaded from the carriers, and the chips that passed the tests are designated as known good dies.
A typical carrier for testing bare chips is described in U.S. Pat. Nos. 5,543,725 and 5,656,945, which are both hereby incorporated by reference in their entireties. In U.S. Pat. No. 5,543,725, a carrier is described which has a cavity to receive a bare chip, and a “head” to establish a good contact between the bare chip and the carrier. In U.S. Pat. No. 5,656,945, a carrier is disclosed which has the shape of a commercial chip package, and a head to press a bare chip into the carrier so as to ensure a good electrical connection between the chip and contact terminals of the carrier. In the test methods using the carriers described in the above references, the loading/unloading of the bare chip must be carried out manually because the loading/unloading cannot be adapted to existing automated chip handling equipment.
SUMMARY OF THE INVENTION
The present invention provides a chip carrier for testing a bare microchip that enables the production of known good dies on a large scale using conventional automated semiconductor handling and test equipment.
According to a first preferred embodiment of the present invention, a carrier includes a carrier body having an open cavity formed in a top surface thereof to receive a bare chip, and a stepped relief formed along two opposing sides of the cavity. Inner contact elements are disposed on the bottom of the cavity to contact selected connection pads on the chip. Outer contact elements, which preferably comprise solder balls, are disposed on a bottom surface of the substrate body and are electrically connected to the inner contact pads. The outer contact elements and substrate body are configured to engage and mate with a test socket for a conventional ball grid array (BGA) packaged chip.
Means for retaining the chip in the carrier include an arcuate pressure clamp having a jaw and a tail rotationally biased about a fixed pin by means of a spring. The jaw is biased toward the bottom of the cavity and the tail extends into the stepped relief. To load a chip in the carrier, the tail is forced down such that the jaw rotates up and away from the cavity about the fixed pin. When the chip is correctly installed in the cavity, the force on the tail of the clamp is removed so that the biasing spring rotates the jaw back toward the floor of the cavity to retain the chip in place and force connection pads on the chip into electrical contact with inner contact elements located on the floor of the cavity.
According to another preferred embodiment of the present invention, the carrier body comprises a lower body having an open cavity to receive a bare chip, an upper body with an opening through it to expose the cavity in the lower body; and means for coupling the upper and lower bodies together and for biasing them apart at a predetermined distance.
Inner contact elements are arrayed on the bottom of the cavity to contact selected connection pads on the chip. Outer contact elements, which preferably comprise leads, are electrically connected to the inner contact elements and are formed on the side surfaces of the lower body. The outer contact elements and carrier bodies are configured to be compatible with a test socket for a conventional lead-type microchip package, such as a Small Outline Package (SOP), a Small Outline J-leaded Package (SOJ), or a Dual In-line Package (DIP).
Means for retaining the chip in the carrier of the second embodiment include a resilient pressure clamp, a clamp deflector and a retainer. The clamp has a multi-toothed, arcuate jaw that extends inwardly toward the chip cavity in the lower body, and a tail that extends outwardly from the cavity and is fixed to the bottom of the upper body. The clamp deflector is positioned below the clamp and outside the cavity. The retainer holds the upper and lower bodies together in their spaced-apart relationship. When the upper body is forced toward the lower body, the clamp deflector flexes the jaw of the clamp upward and outward from the cavity so that the chip can be loaded into the cavity through the opening in the upper body. After the chip is placed in the cavity and the force on the upper body is removed, the coupling means bias the upper body upward, away from the lower body, permitting the jaw of the resilient clamp to flex downwardly and inwardly to engage and retain the chip in place on the floor of the cavity.
The retainer protects the carrier from external forces and enables it to retain its spaced-apart relationship, thereby maintaining a steady pressure on the chip and electrical contact between the chip contacts and those on the carrier. Thus, when it is necessary to apply an external force to the carrier, e.g., to insert it into a test socket, the force is applied to the retainer, and not the body of the carrier.
REFERENCES:
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5656945 (1997-08-01), Cain
Lawrence Don C.
Nguyen Vinh P.
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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