Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-07-17
2007-07-17
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S030000, C702S118000
Reexamination Certificate
active
09887913
ABSTRACT:
A test bus architecture for an integrated circuit chip including a plurality of embedded RAM/register blocks, a corresponding plurality of test modules, and a dedicated test bus. Each RAM/register block is coupled to a corresponding test module, as well as to system circuitry. Each test module is coupled to the test bus. The embedded RAM/register blocks are accessible through the system circuitry during normal operation. During a test mode the embedded RAM/register blocks are accessible through the test modules and test bus. During the test mode, test data values are written to the RAM/register blocks by broadcasting test data values to all of the RAM/register blocks on the test bus. Subsequently, the test data values are read from the RAM/register blocks by individually accessing the RAM/register blocks on the test bus. The test modules are assigned unique addresses, thereby enabling the RAM/register blocks to be addressed during the read operations.
REFERENCES:
patent: 5132973 (1992-07-01), Obermeyer
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5499249 (1996-03-01), Agrawal et al.
patent: 5515540 (1996-05-01), Grider et al.
patent: 5568437 (1996-10-01), Jamal
patent: 5781749 (1998-07-01), Le Quere
patent: 5812469 (1998-09-01), Nadeau-Dostie et al.
patent: 5812562 (1998-09-01), Baeg
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5828856 (1998-10-01), Bowes et al.
patent: 5892777 (1999-04-01), Nesheiwat et al.
patent: 5896396 (1999-04-01), Sanghani et al.
patent: 6101457 (2000-08-01), Barch et al.
patent: 6128758 (2000-10-01), Hall et al.
patent: 6212114 (2001-04-01), Cowles
patent: 6408413 (2002-06-01), Whetsel
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6665817 (2003-12-01), Rieken
Bever, Hoffman & Harm, LLP.
Lamarre Guy J.
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