Test buffer design and interface mechanism for differential...

Details Test buffer design and interface mechanism for differential... Test buffer design and interface mechanism for differential...

2006-06-09

2009-02-03

Tirmmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S025000, C714S043000, C714S056000, C714S726000, C714S727000, C714S740000, C714S734000, C714S821000, C702S117000, C327S001000, C324S512000

Reexamination Certificate

active

07487412

ABSTRACT:
A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

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Kim, Y. et al., “Frequency Detection-Based Boundary-Scan Testing of AC Coupled Nets”, ITC International Test Conference Proceedings, Oct. 30-Nov. 1, 2001, pp. 46-53.

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