Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-10-25
2003-10-28
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S214000, C365S230030
Reexamination Certificate
active
06639859
ABSTRACT:
TECHNICAL FIELD
The technical field is test arrays and methods for testing memory arrays. More specifically, the technical field is test methods and arrays that allow for accurate testing of arrays without undue time or expense.
BACKGROUND
Cross point memory arrays include memory cells located at cross points of horizontal row conductors and vertical column conductors. The memory cells function as the storage elements in cross point memory arrays, and can typically store binary states of either “1” or “0.” The memory cells, the row and column conductors, and other circuitry may be disposed on a substrate. Examples of known cross point memory arrays include non-volatile memories such as one time programmable (OTP) memories, and re-programmable memories. Memory arrays require testing in many circumstances, such as before production on a large scale, and during the development phase of new memory arrays. Testing can involve measuring characteristics of a memory array such as the resistance of memory cells, uniformity of memory cells properties, RH response, resistance-voltage characteristics, and other characteristics.
One approach to testing is to construct a full scale memory array tester including a full integration of driver circuitry, switching circuitry, and other peripheral circuitry. The term “full scale” indicates that the array to be tested includes a number of memory cells that is generally of the same order of magnitude as the number of memory cells that will be included in a final memory product. Using this approach, the characteristics of the test array can be determined by selectively switching the states of the memory cells and by measuring the characteristics of the memory cells under different operating conditions. This testing technique may be effective in determining the characteristics of a test array, but the production of a full scale tester including peripheral circuitry is very expensive and time consuming.
Another technique for testing arrays involves constructing a test array having a full integration of peripheral circuitry in the test array. The characteristics of the test array can therefore be tested using the peripheral circuitry in the array. This technique is also expensive and time consuming, because it involves constructing a completed array during the testing phase.
Another technique for testing memory arrays is to construct a test array that is smaller in scale than the memory array that will be used in the final memory product. The results from the small scale test array are utilized as representative of the results of a full scale memory array. This technique may be unsatisfactory because small scale testing cannot duplicate loading effects, settling times, and other phenomena that occur in full scale arrays. Small scale testing therefore may not be sufficiently accurate for some applications.
A need therefore exists for a test array and a method for accurately testing memory arrays that do not involve excessive cost or delay.
SUMMARY
According to a first aspect, a test array comprises a plurality of row conductors, a plurality of column conductors, and a plurality of memory cells located at cross points of the row and column conductors. The row and the column conductors can include groups of conductors that are electrically coupled, or “ganged” together. The ganged conductors may be coupled to a common terminal. The row and column conductors also include conductors that are connected to individual terminals. Memory cells located at cross points of row and column conductors connected to individual terminals can have their characteristics measured by a test apparatus during testing. The groups of ganged row and column conductors can have common currents or potentials applied to the ganged conductors during testing.
According to the first aspect, the number of terminals of the test array may be relatively small. Therefore, a test apparatus having a limited or a fixed number of probes for connection to the test array can be used to test the array. By selectively ganging together row and/or column conductors, a very large test array can be tested with a test apparatus having a relatively small number of probes.
Also according to the first aspect, the test array can be tested at full scale without undue expense. In addition, a full integration of switching and other circuitry is not required in the test array for testing. Therefore, a test array can be assembled relatively cheaply and quickly, reducing the time and cost for development of new arrays.
Also according to the first aspect, the use of a full scale test array provides more reliable test data than small scale test data because loading effects, settling times, and other characteristics are more accurately predicted by full scale arrays. This feature helps ensure that test data from selected memory cells in the test array are representative of how a full scale final product memory array based on the test array design will perform.
According to a second aspect, a method of testing a test array includes applying an input to a selected row conductor, wherein the selected row conductor crosses a selected memory cell, measuring an output from a selected column conductor, wherein the selected column conductor crosses the selected memory cell, and applying a common input to common terminals of the test array. The common terminals are each coupled to a group of ganged column conductors.
According to the second aspect, the application of a common input to the groups of column conductors allows an expected operational environment of the test array to be simulated. Because the common input can be applied to groups of column conductors through the common terminals, the test array requires fewer terminals to connect to the test apparatus used to test the test array. In addition, the test apparatus requires fewer probes for connection with the test array terminals.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures.
REFERENCES:
patent: 5107459 (1992-04-01), Chu et al.
patent: 5794175 (1998-08-01), Conner
patent: 6456525 (2002-09-01), Perner et al.
patent: 6552409 (2003-04-01), Taussig et al.
Hewlett--Packard Development Company, L.P.
Le Vu A.
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