Test apparatuses for semiconductor integrated circuits

Details Test apparatuses for semiconductor integrated circuits Test apparatuses for semiconductor integrated circuits

2002-09-20

2004-06-22

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S073100, C324S1540PB, C702S118000

Reexamination Certificate

active

06753693

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of priority under 35 U.S.C. §119(a) of Korean Patent Application No. 2001-75868, filed on Dec. 3, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to an apparatus for testing semiconductor integrated circuits and, more particularly, to an apparatus for simultaneously testing a plurality of semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
Generally, a process for fabricating semiconductor integrated circuits comprises steps for testing whether the semiconductor integrated circuit operates properly, and for detecting which portions are not operating correctly.
Test apparatuses for testing steps can typically be categorized as either single test apparatuses or parallel test apparatuses. The single test apparatuses can test only one semiconductor integrated circuit at a time, while the parallel test apparatuses can test a plurality of semiconductor integrated circuits at the same time. Therefore, the parallel test apparatuses can be very useful for production of integrated circuits on a large scale. Such parallel test apparatuses are found in Korean Patent Publication No. 1999-62211 entitled “TEST SYSTEM FOR SEMICONDUCTOR DEVICE,” and Korean Patent Publication No. 2000-17238 entitled “TEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME.”
FIG. 1
illustrates an example of a parallel test apparatus.
Referring to
FIG. 1
, the test apparatus
1
comprises memory sets MS
0
-MSn that correspond to Integrated circuits DUT
0
_DUTn being tested, and store test data T_DATA
0
-T_DATAn for testing the corresponding integrated circuits DUT
0
_DUTn. A driving circuit
30
transfers the test data T_DATA
0
-T_DATAn output from the memory sets MS
0
-MSn to input terminals IN
0
-
1
N
3
of each of the integrated circuits DUT
0
-DUTn. A timing controller
50
controls the driving circuit
30
. Also, the test apparatus
1
comprises a wave generator
60
, an analog unit
70
, and comparators C
0
-Cn. The wave generator
60
and analog unit
70
are described in detail below. The comparators C
0
-Cn correspond to the integrated circuits DUT
0
-DUTh. The comparators C
0
-Cn compare signals, which are output from output terminals OUT
0
-OUT
3
of the integrated circuits DUT
0
_DUTn, with pre-set expected values (expected data), and generate comparison result signals. A controller
10
controls components of the test apparatus
1
. In the test apparatus
1
illustrated in
FIG. 1
, the tested integrated circuits DUT
0
-DUTn each has four input terminals IN
0
-IN
3
as well as four output terminals OUT
0
-OUT
3
.
Each of the memory sets MS
0
-MSn includes four memory units M
0
-M
3
, which correspond to the input terminals IN
0
-IN
3
included in each of the corresponding integrated circuits DUT
0
-DUTn. Each of the memories M
0
-M
3
stores the test data T_DATA
0
-T_DATAn, which will be input to the input terminals IN
0
-IN
3
of the corresponding integrated circuit.
The driving circuit
30
includes sub driving circuits SD
0
-SDn that correspond to the integrated circuits DUT
0
-DUTn. Each of the sub driving circuits SD
0
-SDn includes drivers D
0
-D
3
that correspond to the input terminals IN
0
-IN
3
of the corresponding integrated circuit.
The foregoing conventional test apparatus
1
operates as follows. The test data T_DATA
0
-T_DATAn, which are stored in the memories M
0
-M
3
of each of the memory sets MS
0
-MSn, are output from the respective memories M
0
-M
3
in response to a control signal of the controller
10
.
The test data T_DATA
0
-T_DATAn are transferred from the memory sets MS
0
-MSn to the sub-driving circuits SD
0
-SDn, respectively. Namely, the test data T-DATA
0
Is transferred from the memory set MS
0
to the sub-driving circuit SD
0
; the test data T-DATA
1
is transferred from the memory set MS
1
to the sub driving circuit SD
1
; and the test data T-DATAn Is transferred from the memory set MSn to the sub driving circuit SDn. In response to control signals of the timing controller
50
, the wave generator
60
, and the analog unit
70
, the sub driving circuits SD
0
-SDn transfer the test data T_ATA
0
-T_DATAn, which are input from the memory sets MS
0
-MSn, to the Input terminals IN
0
-IN
3
of the integrated circuits DUT
0
-DUTn being tested.
The timing controller
50
controls the timings of signals output from the drivers D
0
-D
3
in the sub-driving circuits SD
0
-SDn. The wave generator
60
sets the waveforms of signals output from the drivers D
0
-D
3
in the sub-driving circuits SD
0
-SDn. The analog unit
70
sets the voltage levels of signals output from the drivers D
0
-D
3
, which are included in the sub-driving circuits SD
0
-SDn, respectively, and also sets expected values for the comparators C
0
-Cn.
Each of the integrated circuits under test DUT
0
-DUTn receives the test data T_DATA
0
-T_DATAn output from the corresponding sub driving circuits SD
0
-SDn, and generates output signals at the output terminals OUT
0
-OUT
3
in response to the received test data T_DATA
0
-T_DATAn.
Each of the comparators C
1
-Cn compares signals, which are generated at the output terminals OUT
0
-OUT
3
of the corresponding integrated circuits DUT
0
-DUTn, with the expected values, and generates comparison result signals. For example, when the output signals, which are generated at the output terminals OUT
0
-OUT
3
of the integrated circuits DUT
0
-DUTn, are equal to the reference values (i.e., the corresponding integrated circuits DUT
0
-DUTn are operating properly), the comparison result signals are low-level. By comparison, when the output signals, which are generated at the output terminals OUT
0
-OUT
3
of the integrated circuits DUT
0
-DUTn, are not equal to reference values (i.e., the corresponding integrated circuits DUT
0
-DUTn are not operating properly), the comparison result signals are high-level.
Generally, integrated circuits, which are simultaneously tested in the test apparatus
1
, have the same circuit configuration and the same input/output terminals. Therefore, the same test data T_DATA
0
-T_DATAn may be used to test whether each of the integrated circuits is operating properly. However, the conventional test apparatus
1
illustrated in
FIG. 1
has a separate memory set MS
0
, MS
1
, . . . , MSn for each of the integrated circuits DUT
0
-DUTn being tested. Such a test apparatus
1
needs the same number of memory sets as integrated circuits being tested. The additional memory sets cause an increase in size of the test apparatus
1
, and may increase fabrication costs of the test apparatus
1
. Furthermore, as the number of memory sets increases, the controller
10
requires an increased controlling time to read data stored in the memories M
0
-M
3
of the memory sets MS
0
-MSn, i.e., the pattern loading time increases.
SUMMARY OF THE INVENTION
The present invention is directed to a test apparatus, which simultaneously tests multiple semiconductor integrated circuits by applying stored test data to each integrated circuit. The test apparatus includes a set of memory units, each of which stores data used for testing a particular input terminal of each integrated circuit. The test apparatus generates test data for each of the integrated circuits by reproducing the data stored in each of the memory units. Accordingly, the test apparatus need only include a number of memory units equal to the number of input terminals to be tested for each integrated circuit. For example, if four input terminals are being tested for each integrated circuit, only four memory units are required.
The test apparatus includes a sub-test data generator for reproducing the test data stored in the set of memory units in order to generate a reproduced test data set (i.e., sub-test data) for each integrated circuit being tested. Specifically, the sub-test data generator includes one data reproduction unit for each integrated circuit. Each data reproduction unit includes a set of buffers, each of wh

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