Test apparatus with control constant computing device

Details Test apparatus with control constant computing device Test apparatus with control constant computing device

1997-12-16

1999-09-14

Noori, Max

Measuring and testing

Specimen stress or strain, or testing by stress or strain...

Support, holder, or housing for unspecified type electrical...

73805, G01L 100, G01N 300

Patent

active

059525827

ABSTRACT:
A test apparatus is formed of an error area computing device, an upper limit value computing portion and a delay time computing portion. The error area computing device computes an error area corresponding to a difference between waves of a request signal and an output signal to thereby correct control constants for a PID controller based on the error area. The upper limit value computing portion prevents the control constants from being corrected at values higher than upper limit values, and the delay time computing portion computes a phase delay time between the request signal and the output signal. In case the request signal has a higher frequency, the error area is computed as a value from which an error area due to the phase delay time is deducted. Thus, in the test apparatus, the control constants of the PID controller can be optimized for every cycle of an input signal, i.e. the request signal, and in the process of optimizing of the control constants, a bad influence is not exerted to a specimen.

REFERENCES:
patent: 5103671 (1992-04-01), Dyvig
patent: 5327790 (1994-07-01), Levin et al.
patent: 5511431 (1996-04-01), Hinton
patent: 5712431 (1998-01-01), Vilendrer
patent: 5844140 (1998-12-01), Seale

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