Test apparatus, phase adjusting method and memory controller

Details Test apparatus, phase adjusting method and memory controller Test apparatus, phase adjusting method and memory controller

2007-09-04

2007-09-04

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S738000

Reexamination Certificate

active

11180895

ABSTRACT:
An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result and a phase adjustment control circuit for adjusting the timing of the strobe signal based on the comparison result outputted from the logical comparator. The inventive test apparatus further includes a first variable delay circuit for delaying and supplying the strobe signal to the timing comparator and the phase adjustment control circuit sets the delay effected by the first variable delay circuit based on the comparison result outputted from the logical comparator.

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International Search Report for International Application No. PCT/JP2005/005547 mailed Jul. 19, 2005, 3 pages.

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