Test apparatus for static-type semiconductor memory devices

Details Test apparatus for static-type semiconductor memory devices Test apparatus for static-type semiconductor memory devices

1990-07-03

1992-01-07

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 365190, G11C 2900

Patent

active

050797441

ABSTRACT:
A static type semiconductor memory device is provided with a power circuit for a disturb test, in which MOS transistors constituting a memory cell are examined for an abnormal threshold voltage. A P-channel MOS transistor is provided between a power supply, and the memory cells. The P-channel MOS transistor is rendered conductive in the normal mode, allowing the voltage to the memory cells as under normal circumstances. In addition, between the power supply and the memory cells, there is provided a series-connection of a diode-connected N-channel MOS transistor and a P-channel MOS transistor. In the disturb test, this P-channel MOS transistor is rendered conductive. As a result, the supply voltage reduced by the N-channel MOS transistor, or a voltage lower than the supply voltage by the threshold voltage of this N-channel MOS transistor is supplied to the memory cells. By configuring the static type semiconductor memory device in this manner, the time required for the potential difference between the two storage nodes in a memory cell to become small enough, due to a defective transistor in the memory cell, to cause malfunction of the device is reduced. Thus, the time required for the disturb test is shortened.

REFERENCES:
patent: 4267583 (1981-05-01), Suzuki
patent: 4553225 (1985-07-01), Ohe
1977 Mitsubishi Integrated Circuit Databook (LSI), vol. 5, pp. 3-6.

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