Test apparatus and test method

Details Test apparatus and test method Test apparatus and test method

2011-03-08

2011-03-08

Beausoliel, Robert (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S724000

Reexamination Certificate

active

07904765

ABSTRACT:
Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded.

REFERENCES:
patent: 6204681 (2001-03-01), Nagatsuka et al.
patent: 7096396 (2006-08-01), Uesaka et al.
patent: 2003/0016045 (2003-01-01), Tanimura et al.
patent: 07-130200 (1995-05-01), None
patent: 2003-240828 (2003-08-01), None
patent: 2005122490 (2005-05-01), None
Chinese Preliminary Notice of First Office Action dated Mar. 23, 2010, issued for the related Patent Application No. 095116499, and English translation thereof, 18 pages.

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