Test apparatus and test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S754000, C714S769000

Reexamination Certificate

active

07930614

ABSTRACT:
A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.

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patent: 64-008600 (1989-01-01), None
patent: 02-276099 (1990-11-01), None
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