Test apparatus, and method of manufacturing semiconductor...

Details Test apparatus, and method of manufacturing semiconductor... Test apparatus, and method of manufacturing semiconductor...

2006-06-29

2010-02-09

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C365S200000

Reexamination Certificate

active

07661043

ABSTRACT:
A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.

REFERENCES:
patent: 5127097 (1992-06-01), Mizuta
patent: 6249465 (2001-06-01), Weiss et al.
patent: 6553525 (2003-04-01), Shephard, III
patent: 2001/0052093 (2001-12-01), Oshima et al.
patent: 2005/0193233 (2005-09-01), Magliocco et al.

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