Test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

C714S718000, C365S200000, C365S201000

Reexamination Certificate

active

08074130

ABSTRACT:
A test apparatus includes a test section that executes testing of each cell of the memory under test, a fail information storage section that stores fail information in a fail memory; a counting section that counts the number of defective cells in each block, a reading request receiving section that receives a request to read the fail information of each cell, a comparing section that compares the number of defective cells in a block to a predetermined reference number, a converting section that, in a case where the number of defective cells exceeds the predetermined reference value, converts a plurality of consecutive pieces of fail information in a response data string into a value indicating defectiveness, and a compressing section that compresses the response data string and returns a compressed response data string.

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patent: 2007-010605 (2007-01-01), None

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