Test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction

Reexamination Certificate

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Details

C714S744000, C324S765010, C702S069000

Reexamination Certificate

active

06990613

ABSTRACT:
A test apparatus for testing an electronic device includes a pattern generating unit for generating a test pattern to test the electronic device, a reference clock generating unit for generating a reference clock, a timing generator for generating a timing signal, an output signal sampling circuit for sampling the output signal outputted by the electronic device in response to the test pattern at the timing based on the timing signal generated by the timing generator, wherein the timing generator includes a variable delay circuit unit for receiving, delaying and outputting the reference clock, and a delay control unit for controlling the delay amount of the variable delay circuit unit, and the delay control unit controls the delay amount based on the basic timing data and the variable delay amount which is smaller than the basic timing data.

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patent: 6479983 (2002-11-01), Ebiya
patent: 6549000 (2003-04-01), Ebiya
patent: 2004/0208048 (2004-10-01), Doi et al.
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patent: 3066074 (1999-11-01), None
patent: 2000-174838 (2000-06-01), None
patent: 2001-124836 (2001-05-01), None
“A Dynamically Tracking Clock Distribution Chip with Skew Control” by Chengson et al. in 1990 Proceedings of the IEEE Custom Integrated Circuits Conference Publication Date: May 13-16, 1990 pages(s): 15.6/1-15.6/4 NSPEC Accession No.: 3863856.
Patent Abstracts of Japan, Publication No. 2001-124836 dated May 11, 2001, 1 pg.
Patent Abstracts of Japan, Publication No. 06-094796 dated Apr. 8, 1994, 1 pg.
Patent Abstracts of Japan, Publication No. 08-146103 dated Jun. 7, 1996, 1 pg.
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Patent Abstracts of Japan, Publication No. 2000-174838 dated Jun. 23, 2000, 1 pg.
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