Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2002-05-31
2004-02-24
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000
Reexamination Certificate
active
06697755
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a test apparatus such as an LSI tester, and in particular to a test apparatus that stores a decision result of a level of a response signal from a device to be tested.
As the speed of devices to be tested such as LSIs becomes high, tests conducted in LSI testers become high in speed and accuracy. Therefore, it is necessary to apply a test signal to a device to be tested at high speed and effect a decision on a response signal from the device to be tested at high speed and at high accuracy. On the other hand, LSI testers are demanded to have reduced power consumption with due regard to environmental problems and have a larger number of pins in order to reduce the test cost. As a method for constructing a tester that satisfies these demands, it is promising to form the timing system in the tester of CMOS transistors.
FIG. 9
is a block diagram showing one configuration example of LSI testers. Reference numeral
1
denotes a logical value storage circuit,
2
a
and
2
b
analog comparators,
3
an LSI to be tested,
41
a timing generation circuit,
42
a pattern generation circuit,
43
a test signal signal generation circuit,
44
a driver, and
5
an expected value comparison circuit.
With reference to
FIG. 9
, the pattern generation circuit
42
generates predetermined waveform data for testing the LSI
3
to be tested serving as a device to be tested, and supplies the waveform data to the test waveform generation circuit
43
. The test waveform generation circuit
43
generates a test waveform of the LSI
3
to be tested on the basis of the waveform data at timing of a waveform switchover edge (pulse) generated by the timing generation circuit
41
, and supplies the test waveform to the LSI
3
to be tested via the driver
44
. The waveform switchover edge has a period equivalent to a minimum period of the waveform data. In the LSI
3
to be tested, a predetermined test is conducted on the basis of the test waveform, and a response signal REP is output as a result of the test.
The response signal REP is supplied to the analog comparators
2
a
and
2
b,
and compared in level with predetermined thresholds ViH and ViL, respectively, therein. As shown in
FIG. 10
, the response signal REP is a signal that is 5 V at its H (High) level and 0 V at its L (Low) level. The thresholds ViH and ViL are set equal to, for example, 3 V and 1 V, respectively.
As shown in
FIG. 10
, the analog comparator
2
a
outputs a two-valued signal HCMP, which assumes the H level if the response signal REP is at least the threshold ViH and which assumes the L level otherwise. As shown in
FIG. 10
, the analog comparator
2
b
outputs a two-valued signal LCMP, which assumes the H level if the response signal REP is less than the threshold ViL and which assumes the L level otherwise. The two-valued signals HCMP and LCMP are supplied to the logical value storage circuit
1
.
In the logical value storage circuit
1
, logical values (H, L) of the two-valued signals HCMP and LCMP are detected at timing of decision edges (pulses) EH and EL generated by the timing generation circuit
41
, and stored. As shown in
FIG. 11
, the logical value storage circuit
1
in the conventional art includes a D-type FF (flip-flop circuit) la for storing the logical value of the two-valued signal HCMP by using the decision edge EH for HCMP as a clock, and a D-type FF
1
b
for storing the logical value of the two-valued signal LCMP by using the decision edge EL for LCMP as a clock. The logical value of the two-valued signal HCMP is sampled at timing of the decision edge EH and stored in the FF
1
a.
The logical value of the two-valued signal LCMP is sampled at timing of the decision edge EL and stored in the FF
1
b.
Each of the decision edges EH and EL is a pulse having a period equal to that of the waveform switchover edge supplied from the timing generation circuit
41
to the test waveform generation circuit
43
. The decision edges EH and EL are supplied to the logical value storage circuit
1
with a delay after the waveform switchover edge. The delay is equal to a time length between the waveform switchover edge and supply of the two-valued signals HCMP and LCMP to the logical value storage circuit
1
conducted in response to the test waveform output from the test waveform generation circuit
43
. The delay is, for example, 10 nsec. Furthermore, since the response signal REP has a rise characteristic and a fall characteristic as shown in
FIG. 10
, there is a time discrepancy between the rise timing of the two-valued signal HCMP and the fall timing of the two-valued signal LCMP, and there is a time discrepancy between the fall timing of the two-valued signal HCMP and the rise timing of the two-valued signal LCMP. According to the time discrepancy, deskewing for setting a phase relation between the decision edges EH and EL is conducted by using a delay circuit (not illustrated). Furthermore, the decision edge EH is deskewed so as to become in timing either the rise interval or the fall interval during which the level of the two-valued signal HCMP changes. In the same way, the decision edge EL is deskewed so as to become in timing either the fall interval or the rise interval during which the level of the two-valued signal LCMP changes.
Referring back to
FIG. 9
, logical values of the two-valued signals HCMP and LCMP stored in the logical value storage circuit
1
are supplied to the expected value comparison circuit
5
, and compared with expected values supplied from the pattern generation circuit
42
. A result of comparison indicating whether they are coincident with each other is obtained. On the basis of the comparison result, it is determined whether the LSI
3
to be tested is fail or pass as the test result of the LSI
3
to be tested. The expected values output from the pattern generation circuit
42
are based on the waveform data supplied from the pattern generation circuit
42
to the test waveform generation circuit
43
. Generation timing of the expected values is delayed from the waveform data by a time length between generation of the waveform data and supply of logical values to the expected value comparison circuit
5
.
SUMMARY OF THE INVENTION
If the logical value storage circuit
1
samples the two-valued signals HCMP and LCMP by using the FF
1
a
and
1
b
and stores the logical value as described above, the following problems occur.
As a first problem, there is a problem that a difference occurs in the rise characteristic and the fall characteristic of the two-valued signals HCMP and LCMP obtained by the processing of the analog comparators
2
a
and
2
b
and consequently an error occurs in the decision of the test result. This problem will now be described with reference to FIG.
12
. Although the problem will be described with respect to the two-valued signal HCMP, a similar problem occurs in the two-valued signal LCMP as well.
As shown in
FIG. 12
, the two-valued signal HCMP input to the FF
1
a
rises steeply and falls gently. In other words, there is a difference between the rise time and the fall time (transition times) of the waveform. It is now supposed that the FF
1
a
has a threshold of Vth. When a level of the two-valued signal HCMP lower than the threshold Vth is sampled at the decision edge EH, the logical value of the L level is stored in the FF
1
a.
When a level of the two-valued signal HCMP that is equal to or higher than the threshold Vth is sampled at the decision edge EH, the logical value of the H level is stored in the FF
1
a.
A rise interval of the two-valued HCMP is shown in FIG.
12
. It is supposed that the rise is started at t0. It is also supposed that the phase of the decision edge EH is gradually changed from an illustrated position (1) of the two-valued signal HCMP to an illustrated position (2) in a direction indicated by an arrow. When the phase of the decision edge EH arrives at timing when the two-valued signal HCMP becomes the level of the threshold Vth in the rise interval, the logical va
Fukuzaki Masashi
Motoki Nobuo
Oonishi Fujio
Orihashi Ritsuro
Shinbo Kenichi
Hoff Marc S.
Miller Craig Steven
LandOfFree
Test apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3346745