Test and observe mode for embedded memory

Details Test and observe mode for embedded memory Test and observe mode for embedded memory

1999-07-13

2003-03-18

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S718000

Reexamination Certificate

active

06535999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of testing semiconductor memory devices and, more particularly to a test and observe mode for an embedded dynamic random access memory (DRAM) device.
2. Description of the Related Art
Dynamic random access memories (DRAMs) contain an array of individual memory cells. Typically, each DRAM memory cell comprises a capacitor for holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either high voltage or low voltage (representing, e.g., a logical “1” or a logical “0,” respectively). Data can be stored in memory during write operations or read from memory during read operations.
Refresh, read, and write operations in present-day DRAMs are typically performed for all cells in one row simultaneously. Data is read from memory by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to digit or bit lines which define the columns of the array. When a particular word line and bit line are activated, a sense amplifier detects and amplifies the data in the addressed cell by measuring the potential difference on the activated bit line corresponding to the content of the memory cell connected to the activated word line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc. and incorporated by reference herein.
An embedded DRAM resides on a complex semiconductor circuit containing significant amounts of both DRAM and logic units (for example, a processor). This results in a compact design with minimal propagation distances between the logic units and the memory cells. Embedded DRAM also offers the advantages of simpler system-level design, fewer packages with fewer pins, reduced part count, and lower power consumption. This reduction in external circuit connections increases the efficiency of the DRAM and the overall logic processing device or application. For example, the bandwidth, the number of input and output pins, of the DRAM can increase because less circuitry is required to operate the DRAM. Speed also increases since the logic and control signals, as well as the input and output data, travel shorter distances.
Since the function of the embedded DRAM is very critical to the overall integrated circuit (IC) it resides on, it is extremely important to verify that the embedded DRAM survives the manufacturing process and still operates as it was intended to. Typically, the embedded DRAM is tested by writing a known pattern or series of patterns into the DRAM, reading the pattern out of the DRAM and then comparing the read pattern to the known pattern. Any discrepancies would indicate that memory cells within the DRAM were corrupted and need to be repaired.
Currently, embedded DRAM is tested by one of two methods. The first method utilizes an external testing device which is programmed to exercise the memory cells of the embedded DRAM as described above. The testing device supplies the necessary address, data and control signals to the embedded DRAM through the integrated circuit's pads or package pins. The contents of the memory cells within the DRAM are read by the testing device, compared to the test data and evaluated to determine if there were any errors.
The second method is performed internally on the integrated circuit and is often referred to as a built-in-self-test (BIST). A typical BIST circuit utilizes pattern generators to generate test data and the addresses of the to-be-tested memory cells. The BIST circuit includes logic to write the test patterns into the addressed cells of the DRAM, read the patterns out of the cells and evaluate the patterns to determine if any of the DRAM memory cells are defective.
Although these methods work well to determine if the embedded DRAM is capable of storing and outputting data, these methods do not indicate how the DRAM is being accessed. That is, the methods do not determine how the IC's logic is accessing and controlling (also known in the art as “driving”) the embedded DRAM. In the first method, the external tester is driving the DRAM, not the IC's logic and therefore, a determination of how the DRAM is being driven by the logic can not be made. In the second method, a BIST circuit is driving the embedded DRAM and the information on how the DRAM is being accessed is incapable of being properly tested, determined or reported.
Determining how the embedded DRAM is being accessed by the circuit's logic is very important and is particularly useful to test and debug the logic during a design stage. Accordingly, there is a need and desire for an embedded DRAM testing scheme that determines how the DRAM is being accessed.
SUMMARY OF THE INVENTION
The present invention provides an embedded DRAM testing scheme that determines how the DRAM is being accessed.
The above and other features and advantages of the invention are achieved by a method and apparatus that tests and observes how an embedded DRAM is being accessed by a logic circuit controlling the DRAM. The test and observe method and apparatus pipes the outputs of the logic, which is used as inputs to the embedded DRAM, to an observation device. The outputs of the logic device are then observed at the observation device to determine how the DRAM is being accessed. In addition, information concerning what data is being trapped and when may be output to the observation device to determine setup and hold times for the DRAM.


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