Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2002-09-20
2008-09-23
Baderman, Scott T. (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S727000
Reexamination Certificate
active
07428661
ABSTRACT:
A test and debug processor capable of initiating, commanding and executing JTAG-bus functions without the involvement of an external CPU. The processor includes a JTAG-bus controller with a JTAG port coupled to it. The JTAG-bus functions are encoded in instructions and stored in a memory structure. The processor instructions are then fetched and executed directly by the JTAG-bus controller without software interpretation. The instructions optionally includes JTAG-bus end state, function duration information, information about the location of the data to be sent out to the test object and a location to store the information received from the test object. Optionally, the test and debug processor can directly access any memory structure to fetch or store test data objects by adding a memory bus-controller interface to the processor. The ability to execute arithmetic and logic operation and register transfer operations on test data can be added using an ALU.
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Baderman Scott T.
Contino Paul F.
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