Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-07-12
2011-07-12
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S025000, C714S029000, C714S030000, C714S042000, C714S043000, C714S045000, C714S048000, C714S052000, C714S712000, C714S713000, C714S715000, C714S719000, C714S723000, C714S733000, C714S734000, C714S736000, C714S741000, C714S746000, C714S799000, C710S316000, C702S117000, C703S013000, C703S014000, C703S015000, C703S023000, C716S030000, C716S030000, C365S201000
Reexamination Certificate
active
07979759
ABSTRACT:
A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
REFERENCES:
patent: 4034195 (1977-07-01), Bates
patent: 4376306 (1983-03-01), Giusto
patent: 4468770 (1984-08-01), Metcalf et al.
patent: 4631686 (1986-12-01), Ikawa et al.
patent: 4644498 (1987-02-01), Bedard et al.
patent: 4775979 (1988-10-01), Oka
patent: 5321813 (1994-06-01), McMillen et al.
patent: 5513135 (1996-04-01), Dell et al.
patent: 6067262 (2000-05-01), Irrinki et al.
patent: 6070256 (2000-05-01), Wu et al.
patent: 6119181 (2000-09-01), Vorbach et al.
patent: 6147967 (2000-11-01), Ying et al.
patent: 6297995 (2001-10-01), McConnell et al.
patent: 6308286 (2001-10-01), Richmond et al.
patent: 6337817 (2002-01-01), Horiguchi et al.
patent: 6338154 (2002-01-01), Kim
patent: 6367042 (2002-04-01), Phan et al.
patent: 6381685 (2002-04-01), Dell et al.
patent: 6518593 (2003-02-01), Takabayashi et al.
patent: 6526461 (2003-02-01), Cliff
patent: 6531339 (2003-03-01), King et al.
patent: 6789212 (2004-09-01), Klingman
patent: 6895528 (2005-05-01), Cantwell et al.
patent: 6931564 (2005-08-01), Goodman et al.
patent: 6973605 (2005-12-01), Templeton et al.
patent: 7013416 (2006-03-01), Whetsel
patent: 7058918 (2006-06-01), Abramovici et al.
patent: 7069494 (2006-06-01), Cargnoni et al.
patent: 7154723 (2006-12-01), Warnakulasooriya et al.
patent: 7168005 (2007-01-01), Adams et al.
patent: 7178076 (2007-02-01), Zarrineh et al.
patent: 7181659 (2007-02-01), Bravo et al.
patent: 7277346 (2007-10-01), Rahim et al.
patent: 7299313 (2007-11-01), Gower et al.
patent: 7334149 (2008-02-01), Wu
patent: 7353316 (2008-04-01), Erdmann
patent: 7362697 (2008-04-01), Becker et al.
patent: 2002/0024455 (2002-02-01), Abbiate et al.
patent: 2002/0075982 (2002-06-01), Doblar
patent: 2003/0074619 (2003-04-01), Dorsey
patent: 2003/0185251 (2003-10-01), Ichino et al.
patent: 2004/0180455 (2004-09-01), Marr
patent: 2004/0190331 (2004-09-01), Ross et al.
patent: 2004/0216026 (2004-10-01), Ferraiolo et al.
patent: 2004/0250181 (2004-12-01), Vogt et al.
patent: 2005/0138496 (2005-06-01), Brennan et al.
patent: 2005/0174138 (2005-08-01), Marr
patent: 2005/0210185 (2005-09-01), Renick
patent: 2005/0223196 (2005-10-01), Knowles
patent: 2005/0246597 (2005-11-01), Whetsel
patent: 2006/0036827 (2006-02-01), Dell et al.
patent: 2006/0095620 (2006-05-01), Dreps et al.
patent: 2006/0107175 (2006-05-01), Dell et al.
patent: 2006/0179369 (2006-08-01), Bravo et al.
patent: 2006/0179394 (2006-08-01), O'Neill et al.
patent: 2006/0218455 (2006-09-01), LeClair et al.
patent: 2006/0277363 (2006-12-01), Qiu et al.
patent: 2007/0011562 (2007-01-01), Alexander et al.
patent: 2007/0075734 (2007-04-01), Ramos et al.
patent: 2007/0204190 (2007-08-01), Hesse et al.
patent: 2007/0283223 (2007-12-01), Dell et al.
patent: 2007/0288816 (2007-12-01), Nakanishi
patent: 2007/0300129 (2007-12-01), Dell et al.
patent: 2008/0005644 (2008-01-01), Dell
patent: 2008/0022186 (2008-01-01), Co et al.
patent: 2008/0028345 (2008-01-01), Suri et al.
patent: 2008/0046774 (2008-02-01), Hirai et al.
patent: 2008/0046796 (2008-02-01), Dell et al.
patent: 2008/0065938 (2008-03-01), Cowell et al.
patent: 2008/0115137 (2008-05-01), Gower et al.
patent: 2010/0153794 (2010-06-01), Jeddeloh
patent: 1622020 (2006-02-01), None
patent: 02-307254 (1990-12-01), None
patent: 03-234125 (1991-10-01), None
patent: 09-261210 (1997-10-01), None
G. Boudon et al., “Novel Bus Reconfiguration Scheme With Spare Lines”, IBM Technical Bulletin, May 1987, pp. 5590-5593.
Sunggu Lee, et al., “Probabilistic Diagnosis of Multiprocessor Systems”, ACM Computing Surveys, Mar. 1994, pp. 121-139, vol. 26, No. 1.
Alan Charlesworth et al., “The Starfire SMP Interconnect”, 1997, pp. 1-20, ACM.
Daniele Rossi et al., “New ECC for Crosstalk Impact Minimization”, Jul./Aug. 2005, pp. 340-348 IEEE CS and the IEEE CASS.
Smitha Shyam et al., “Ultra Low-Cost Defect Protection for Microprocessor Pipelines”, ASPLOS' 06, Oct. 21-25, 2006, pp. 73-82, ACM, San Jose, California, USA.
D.M Berger et al., “High-Speed source-synchronous interface for the IBM System z9 processor” IBM J. Res & Dev., Jan. 2007, pp. 53-64, vol. 51, No. 1/2, IBM.
FBDIMM: Architecture and Protocal, Jan. 2007, JESD206, JEDEC Solid State Technology Association, Arlington, VA USA.
Bravo Elianne A.
Carnevale Michael J.
Gower Kevin C.
Van Huben Gary A.
Ziebarth Donald J.
Cantor & Colburn LLP
International Business Machines - Corporation
Trimmings John P
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