Ternary bit line signaling

Details Ternary bit line signaling Ternary bit line signaling

2007-01-02

2007-01-02

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

10791834

ABSTRACT:
A memory device is disclosed having a plurality of dual-bit addressable memory cells. In each memory cell, a first storage circuit for storing a first bit may be activated or de-activated depending upon the state of a second bit stored in a second storage circuit. The second bit may be considered to be a “don't care” bit, because depending upon the state of the second bit, the first bit may be irrelevant in that it cannot be read. Thus, each memory cell may effectively store three states: zero, one, and don't care.

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Hiroki Uchiyama et al., “Temary Content Addressable Memory With Hamming Distance Search Functions”, dated prior to filing of present application.
Igor Arsovski, et al., “A Temary COntent-Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme”, IEEE Journal of Solid-State Circuits, vol. 38, No. 1, Jan. 2003. pp. 155-158.

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