Ternary based shifter that supports multiple data types for shif

Details Ternary based shifter that supports multiple data types for shif Ternary based shifter that supports multiple data types for shif

1996-10-31

1998-10-13

Ngo, Chuong Dinh

Boots, shoes, and leggings

G06F 700

Patent

active

058222316

ABSTRACT:
A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block. A decode of the block select signals are coupled to the second level shifter as the second level shift signal and a decode of the bit select signals are coupled to the first level shifter as the first level shift signal. Therefore, the block select signals specify shifts of 0, 3, or 6 bits and the bit select signals specify shifts of 0, 1 or 2 bits, to specify a total shift of between 0 and 8 bits. The nine bit two level modular shifter can be used to create a wider shift comprised of three levels. The third level shifter which includes 4 9-bit 4:1 multiplexers, receives thirty six input bits and third level shift signals. The third level shifter outputs the thirty six input bits shifted by 0, 9, 18, or 27, which are then supplied to four two level 9 bit shifters to provide a full 36 bit shift/rotate operation.

REFERENCES:
patent: 4839839 (1989-06-01), Tokumaru et al.
patent: 4931925 (1990-06-01), Utsumi et al.
patent: 5130940 (1992-07-01), Omote
patent: 5671166 (1997-09-01), Omote
Mead and Conway, "Introduction to VLSI Systems", pp. 159-161, Addison-Wesley Publishing Company, Philippines (1980).

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