Termination structure for high speed, high pin density chips

Details Termination structure for high speed, high pin density chips Termination structure for high speed, high pin density chips

2000-02-23

2002-11-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S090000, C326S021000, C333S02200F, C333S012000, C333S032000

Reexamination Certificate

active

06486696

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high speed, high pin density chips, and more particularly, to a termination structure for a high speed, high pin density chips which reduces the effects of signal ringing, unwanted oscillations, overshoots and undershoots, while consuming little extra power.
2. Description of the Related Art
In a high speed and high pin density package device (HSHD) which has on the order of several hundred pins, the parasitic parameters of the HSHD package device, such as the parasitic capacitance, inductance, mutual inductance and resistance become prominent and result in large cross talk and oscillation of the input signals. This cross talk and oscillation lower the performance of the HSHD device.
For example, consider the example in
FIG. 1
of a high speed and high density package device (HSHD)
10
driving another HSHD
20
device through a PCB trace (T
1
-T
N
)
30
. When the output signals
12
from the corresponding pins Pin
1
-Pin
N
of the source HSHD
10
pass through the source high density package
40
, the output signals
14
become somewhat irregular. Then the output signals
14
pass through the PCB trace (T
1
-T
N
)
30
through the destination high density package
50
to the input pins Pin
1
-Pin
N
of the destination HSHD device
20
. Due to the parasitic effects caused in the process of passing through the input pins' package R
1
-R
N
, the signals
16
exhibit oscillation, large glitches on the rising edge of the signals, and large overshoots and undershoots. The glitches, overshoots and undershoots greatly increase the setup process time of the input signal's valid logic level; in fact a large amplitude overshoot and/or undershoot may prevent the valid logic level from being set up during an entire clock cycle. Large overshoots may also damage the input CMOS logic.
The arrangement in
FIG. 1
may also introduce signal ringing. Ringing results from signal reflection in the PCB trace (T
1
-T
N
)
30
. There have been numerous attempts to reduce or eliminate signal ringing by address termination when the output signal of a device travels through a PCB trace to the input of another device. Source terminations (resistors) and end terminations (resistors and capacitors) have been used to attempt to solve the signal ringing problem.
FIG. 1
is an example of a source termination structure. In
FIG. 1
, resistors R
E1
, . . . , R
EN
18
act as the source termination of the interface between HSHD
10
and HSHD
20
.
FIG. 2
is an example of an end termination structure. In
FIG. 2
, resistors Rt
1
. . . Rt
N
act as the end termination of the interface between HSHD
10
and HSHD
20
.
FIGS. 3
a
-
3
c
illustrate several end termination structures.
FIG. 3
a
illustrates the structure in
FIG. 2
, while
FIG. 3
b
illustrates a dual resistor (Rt
M
and Rt
N
) configuration (similar to the configuration used in U.S. Pat. No. 5,519,353 to Rainal).
FIG. 3
c
illustrates an alternative resistor Rt
N
and capacitor C
N
configuration. In
FIGS. 1 and 2
, the packages
40
and
50
are shown as being connected with a vertical line, in order to illustrate that the packages
40
and
50
are related to each other by mutual inductance.
As set forth above, the termination structures in
FIGS. 3
a
-
3
c
are used to solve signal ringing in PCB traces, such as PCB trace (T
l
-T
N
)
30
. However, other problems which result from the configuration of
FIG. 1
, include unwanted oscillations, glitches, undershoots and overshoots. These problems may be caused by the package
50
of the HSHD input device
20
itself. The termination structures in
FIGS. 3
a
-
3
c
reduce, to some degree, the signal oscillations, glitches, undershoots and overshoots. However, the structures shown in
FIG. 3
b
and
3
c
consume extra power, and the values of the resistor Rt
N
and capacitor C
N
in the structure of
FIG. 3
c
are difficult to choose when large parasitic effects exist in the package
50
of the HSHD input device
20
.
For example, in
FIG. 3
c
, if a signal of a certain frequency propagates from left (input) of the PCB trace Tn to right (output), a multiplying factor relative to the signal frequency, namely (1+j&ohgr;RC)/(1+j&ohgr;)(Ro+R)C), where Ro is the impedance of the PCB trace Tn, R is the resistance of Rtn, C is the capacitance of Cn and &ohgr; is the frequency of the signal may be added to the output signal. This results in the introduction of a pole and a zero evident in a Pole-Zero Plot, which may cause the output signal to oscillate. Another problem introduced by the arrangement in
FIG. 3
c
is that the multiplying factor is usually smaller than 1, which reduces the valid input logic voltage level. This condition is worsened if R≦Ro.
FIG. 3
a
and
FIG. 3
b
also introduce this valid logic voltage level problem.
The signal oscillations, glitches, undershoots and overshoots problems caused by the package
50
of the HSHD input device
20
in
FIG. 1
are illustrated in
FIGS. 4
a
-
4
d
.
FIGS. 4
a
-
4
d
illustrate the input signals
16
at Pin
M
with the circuitry illustrated in FIG.
1
. In particular,
FIG. 4
a
illustrates the fastest operation condition of the HSHD input device
10
, where the input signals
16
are propagated at the fastest speed and the largest oscillation or overshoot and undershoot may occur. This is termed the “worst case fast” condition. As illustrated between time
16
and
18
in
FIG. 4
a
, large oscillations are apparent.
FIG. 4
c
illustrates the leading edge of the waveform, including the large oscillations, of
FIG. 4
a
in more detail.
FIG. 4
b
illustrates a counterpart waveform for the waveform illustrated in
FIG. 4
a
. In particular,
FIG. 4
b
illustrates the slowest operation condition or “worst case slow” condition of the HSHD input device
10
, where the input signal
16
s
are propagated at the slowest speed, and the smallest oscillation, overshoot, or undershoot may occur. As illustrated between time
20
and
22
in
FIG. 4
b
, large oscillations are apparent.
FIG. 4
d
illustrates the leading edge of the waveform, including the large oscillations, in
FIG. 4
b
in more detail.
SUMMARY OF THE INVENTION
The present invention provides a novel termination structure, which reduces the problems described above with conventional PCB traces between HSHD devices and their packages.
In particular, in one embodiment of the present invention, a resistor is inserted in series between a PCB trace and an input pin of the destination high density package. The series resistor, acting as a type of end termination, positively alters the waveforms of the signals input to the destination high speed density package. In particular, glitches and ringing after the input pin package or at the output of the destination high density package (at the gate for a CMOS transistor) are reduced. Overshoots and undershoots are also reduced. As a result, the input signals are usable and the interface between HSHD devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable.
An additional advantage of the present invention is that the inserted series resistor consumes very little extra power (except for a little thermal energy). The inserted series resistor may increase the rise/fall times of the input signals very slightly, but this increase is much smaller than the increase caused by the conventional glitches, overshoots and undershoots. Therefore, if a signal is one of the input signals to which an inserted series resistor is added, the value selected for the inserted resistor for the input signal may depend on both overshoot and undershoot tolerances of the device and on the rise/fall time requirement of the signals.


REFERENCES:
patent: 5111080 (1992-05-01), Mizukami et al.
patent: 5227677 (1993-07-01), Furman
patent: 5495186 (1996-02-01), Kanazawa et al.
patent: 5519353 (1996-05-01), Rainal
patent: 5604450 (1997-02-01), Borkar et al.
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