Wave transmission lines and networks – Automatically controlled systems – Impedance matching
Reexamination Certificate
1999-05-27
2001-06-19
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Automatically controlled systems
Impedance matching
C333S032000, C333S033000
Reexamination Certificate
active
06249193
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of electronic devices and, more particularly, to a system and structure for impedance matching in very high speed input-output (I/O) chip interfacing to improve performance and reliability of I/O chips and systems that contain I/O chips.
BACKGROUND OF INVENTION
One of the most important aspects in integrated chip system design is the interface considerations for very short channel Complementary Metal-Oxide-Semiconductor (CMOS) devices in high-speed applications. Beginning with the driving circuit, an on-chip voltage swing of ground to Vdd (internal power supply) must be communicated off-chip to external devices. The path from the driver output to the output pad involves capacitive coupling effects to other on-chip signals. Moreover, the chip packaging system adds inductances to the circuit. The external signals must then traverse some interconnect (or transmission line), whether card traces or multi-chip module (MCM) connections. The signals are subject to additional deformations at this point due to transmission line effects introduced by the interconnects. The use of external decoupling capacitors to stabilize the card power supply provided to the chip is known in the art. For low-impedance card power plane connections, these external capacitors do not reduce the on-chip simultaneous switching noise of the driver circuit.
Transmission line effects become significant when the round trip propagation delay from the sending chip to the receiving chip is greater than the rise time of the transmitted signal. This condition is almost always met for modern CMOS-based digital systems. When this is the case, reflections occur on the signal line due to impedance mis-matches between the source, the transmission line, and the load. These reflections are superimposed on the transmitted signal, causing significant overshoot, undershoot, and system-wide noise. These conditions can cause both performance problems and reliability problems.
The performance problem is a reduction in the valid-data window of transmitted pulses with respect to the system clock. The reliability problem involves devices with ultra-thin gate dielectric layers, less than 5 nm thickness, for which overshoots and undershoots can have a significant effect in reducing the effective useful life of the thin gate dielectric. This can lead to catastrophic breakdown. The voltage overshoots and undershoots can also cause latch-up in CMOS devices leading to serious reliability problems. For high speed CMOS applications where the data rates are in the range of 1 GHz to 10 GHz and above, these performance and reliability problems can cause severe design limitations and prove costly.
The deficiencies of conventional, high-speed input-output interfaces show that a need exists for improvement. To overcome the shortcomings of conventional systems, a new system and structure for impedance matching in high-speed input-output chip interfacing is provided. It is an object of the present invention to provide a system and structure to achieve impedance matching at a driver circuit output, thereby preventing and not merely compensating for high voltage transients (overshoots) and low voltage transients (undershoots). It is another object of the present invention to provide a system and structure which can be manually adjusted to provide impedance matching at a driver circuit output during system set-up. It is yet another object of the present invention to provide an economical and manufacturable system and structure which can be manually adjusted to provide impedance matching at a driver circuit output for actual operating conditions of a specific system.
It is still another object of the present invention to provide a system and structure capable of automatically adjusting to provide impedance matching at a driver circuit output when operating conditions cause changes to the system.. Another object of the present invention is to provide a control circuit for an impedance matching system which detects overshoots and undershoots on the driver circuit output and automatically provides a control voltage to an adjustment mechanism to adjust the length of an adjustable-length transmission line providing impedance matching based on actual overshoots and undershoots. Still another object of the present invention is to provide an impedance matching system capable of performing its functions under a wide range of values for the various components comprising both the on-chip driver circuit and the off-chip interface circuitry.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a process and structure for an impedance matching network. The structure includes an adjustable-length transmission line located between the driver circuit and the receiver circuit (load) on the system printed circuit board (card). The adjustable-length transmission line is comprised of two conductive stripes connected in parallel with an input-output driver circuit at one end, electrically isolated at the opposite end, and short circuited by a movable stub intermediate of the ends. The adjustable length transmission line is located on the system printed circuit board between the driver circuit and the receiver circuit. Optionally, the impedance matching network may further comprise an adjustment mechanism and a control circuit.
The impedances at the driver circuit output are matched by adjusting the length of the adjustable-length transmission line such that the composite reactance of the load, the transmission line between the driver circuit chip and the load, the connections, and the adjustable-length transmission line equals the converse of the driver reactance. In a first embodiment, the length of the adjustable-length transmission line can be set or adjusted manually at system set-up, such as by a systems engineer or operator. In order to adjust the adjustable-length transmission line, the systems engineer or operator observes the waveform using electronic measuring equipment such as an oscilloscope. The position of the moveable stub is manually adjusted until the magnitude of undershoots and overshoots as viewed on the electronic measuring equipment is minimized.
In a second embodiment, the length of the adjustable-length transmission line is adjusted by the adjustment mechanism. The adjustment mechanism comprises an elecromagnetic coil, a moveable magnetic core, and a return spring. The electromagnetic coil creates a magnetic field proportional to a control current from the control circuit. The magnetic field provides a force to the moveable magnetic core acting in a first direction. The return spring provides a force to the moveable magnetic core acting in a second direction opposite to the first direction. The moveable magnetic core is attached to the moveable stub whose position determines the length of the adjustable-length transmission line.
The control circuit generates a control current which varies in response to high and low transient voltages on the driver circuit output. In the second embodiment, the control circuit comprises a positive detect circuitry and a negative detect circuitry, each of which provides a high (up) pulse to a counter when triggered by a transient, and a CLK down generator which provides a low (down) pulse to the counter as a function of the system clock. Both the positive detect circuitry and the negative detect circuitry are self-resetting.
In the second embodiment, the control circuit further comprises a quantity of “n” N-type field effect transistors connected in parallel between the adjustment mechanism of the adjustable length transmission line and the system ground. The transistors have control gates connected to an n-bit counter which is incrementally increased by the positive detect circuitry when an overshoot occurs on the driver circuit output and by the negative detect circuitry when an undershoot occurs on the driver circuit output. Thus, the number of transistors drawing current and th
Abadeer Wagdi W.
Connor John
Hansen Patrick R.
Glenn Kimberly E
International Business Machines - Corporation
Pascal Robert
Ratner & Prestia
Towsend, Esq. Tiffany L.
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