Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-04-19
2005-04-19
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000
Reexamination Certificate
active
06882174
ABSTRACT:
It is intended to provide a terminal control device and a universal serial bus system capable of achieving stable system operation wherein the termination control device controls termination considering propagation delay time required for bus voltage level to shift to termination voltage when a universal serial bus system is terminated and an erroneous detection due to propagation delay time of voltage level shifting is avoided, accordingly. A pull-up start signal PU is inputted to a mask counter11, timing operation is conducted in a manner of count operation. As a result of count operation, mask count signals MC are outputted to a comparator13. Masking-time setting signals SC are inputted to the comparator13. The mask count signals MC and the masking-time setting signals SC are compared to calculate a predetermined length of masking time that begins with start of pull-up. During this masking time, detection of SE0state or bus-reset state is masked. Thereby, there can be avoided erroneous detection of an SE0during transition period after start-up of the system, and termination control can surely be conducted.
REFERENCES:
patent: 6166563 (2000-12-01), Volk et al.
patent: 6762620 (2004-07-01), Jang et al.
Universal Serial Bus Specification, Revision 2.0, Apr. 27, 2000 (Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips), pp. viii and 144-155.
Cho James H.
Fujitsu Limited
Staas & Halsey , LLP
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