Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Patent
1995-10-27
1998-03-17
Hudspeth, David R.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
326 30, H03K 1716
Patent
active
057291527
ABSTRACT:
A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
REFERENCES:
patent: 3585378 (1971-06-01), Bouricius et al.
patent: 3651473 (1972-03-01), Faber
patent: 3761879 (1973-09-01), Brandsma et al.
patent: 3803562 (1974-04-01), Hunter
patent: 3849872 (1974-11-01), Hubacher
patent: 3983537 (1976-09-01), Parsons et al.
patent: 4007452 (1977-02-01), Hoff, Jr.
patent: 4038648 (1977-07-01), Chesley
patent: 4063225 (1977-12-01), Stewart
patent: 4071887 (1978-01-01), Daly et al.
patent: 4092733 (1978-05-01), Coontz et al.
patent: 4132869 (1979-01-01), Knox
patent: 4188670 (1980-02-01), Hsia
patent: 4215430 (1980-07-01), Johnson, Jr.
patent: 4227045 (1980-10-01), Chelcun et al.
patent: 4319356 (1982-03-01), Kocol et al.
patent: 4329685 (1982-05-01), Mahon et al.
patent: 4355387 (1982-10-01), Portejoie et al.
patent: 4379327 (1983-04-01), Tietjen et al.
patent: 4400794 (1983-08-01), Koos
patent: 4407014 (1983-09-01), Holtey et al.
patent: 4414480 (1983-11-01), Zasio
patent: 4438352 (1984-03-01), Mardkha
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4494196 (1985-01-01), Greer
patent: 4605928 (1986-08-01), Georgiou
patent: 4615017 (1986-09-01), Finlay et al.
patent: 4627058 (1986-12-01), Moriyama
patent: 4630355 (1986-12-01), Johnson
patent: 4639861 (1987-01-01), Appiano et al.
patent: 4639933 (1987-01-01), Howell et al.
patent: 4646298 (1987-02-01), Laws et al.
patent: 4649384 (1987-03-01), Sheafor et al.
patent: 4653050 (1987-03-01), Vaillancourt
patent: 4663758 (1987-05-01), Lambarelli et al.
patent: 4667328 (1987-05-01), Imran
patent: 4680780 (1987-07-01), Agoston et al.
patent: 4703436 (1987-10-01), Varshney
patent: 4707808 (1987-11-01), Heimbigner
patent: 4719621 (1988-01-01), May
patent: 4736365 (1988-04-01), Stern
patent: 4823363 (1989-04-01), Yoshida
patent: 4847615 (1989-07-01), MacDonald
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 4872137 (1989-10-01), Jennings, III
patent: 4876700 (1989-10-01), Grindahl
patent: 4881232 (1989-11-01), Sako et al.
patent: 4890224 (1989-12-01), Fremont
patent: 4906987 (1990-03-01), Venaleck et al.
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4926382 (1990-05-01), Sakui et al.
patent: 4943914 (1990-07-01), Kubo
patent: 4943966 (1990-07-01), Giunta et al.
patent: 4955020 (1990-09-01), Stone et al.
patent: 4970724 (1990-11-01), Yung
patent: 4974048 (1990-11-01), Chakravorty et al.
patent: 4980765 (1990-12-01), Kudo et al.
patent: 4984192 (1991-01-01), Flynn
patent: 4985895 (1991-01-01), Pelkey
patent: 5001712 (1991-03-01), Splett et al.
patent: 5020020 (1991-05-01), Pomfret et al.
patent: 5021985 (1991-06-01), Hu et al.
patent: 5043820 (1991-08-01), Wyles et al.
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5055897 (1991-10-01), Canepa et al.
patent: 5077596 (1991-12-01), Inoue
patent: 5077737 (1991-12-01), Leger et al.
patent: 5077738 (1991-12-01), Larsen et al.
patent: 5103424 (1992-04-01), Wade
patent: 5111271 (1992-05-01), Hatada et al.
patent: 5111434 (1992-05-01), Cho
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5128737 (1992-07-01), van der Have
patent: 5131015 (1992-07-01), Benjaram et al.
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5159273 (1992-10-01), Wright et al.
patent: 5161152 (1992-11-01), Czerwiec et al.
patent: 5187779 (1993-02-01), Jeddeloh et al.
patent: 5204836 (1993-04-01), Reed
patent: 5206832 (1993-04-01), Yamaguchi et al.
patent: 5214657 (1993-05-01), Farnworth et al.
patent: 5218686 (1993-06-01), Thayer
patent: 5227677 (1993-07-01), Furman
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5247522 (1993-09-01), Reiff
patent: 5252507 (1993-10-01), Hively et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5261077 (1993-11-01), Duval et al.
patent: 5265216 (1993-11-01), Murphy et al.
patent: 5268639 (1993-12-01), Gasbarro et al.
patent: 5278967 (1994-01-01), Curran
patent: 5311083 (1994-05-01), Wanlass
patent: 5329174 (1994-07-01), Chiang
patent: 5329559 (1994-07-01), Wong et al.
patent: 5371420 (1994-12-01), Nakao
patent: 5379258 (1995-01-01), Murakami et al.
patent: 5402388 (1995-03-01), Wojcicki et al.
patent: 5434996 (1995-07-01), Bell
patent: 5539328 (1996-07-01), Mirov et al.
"Active Terminators for CMOS Drivers", IBM Tech. Discl. Bull., vol. 32, No. 4A, pp. 393-395, Sep. 1989.
Peter van Zant, Microchip, A Practical Guide to Semiconductor Processing, 1st Ed., Semiconductor Services, San Jose, CA 1986, p. 8.
MacDonald et al, "Dynamic RAMs 200mb Wafer Memory," IEEE ISSCC, Feb. 17, 1989, pp. 240-241 and 350.
Cavil et al., "Wafer-Scale Integration," Microelectronics Manufacturing Technology, May, 1991, pp. 55-59.
Ron Iscoff, "Characterizing Quickturn ASICs: It's Done with Mirrors" semiconductor International, Aug. 1, 1990, pp. 68-73.
Takai et al., "250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture," IEEE Jnl of Solid State circuirts, vol. 29, No. 4, Apr. 1994, pp. 426-431.
Fujii, et al., "A 50-.mu.A Standby 1M.times.1/256K.times.4 CMOS DRAM with High-Speed Sense Amplifier," IEEE Jnl of Solid State Circuits, vol. SC-21, No. 5, oct., 1986, pp. 643-647.
Yamashita, Koichi and Shohei Ikehara, "A Design and Yield Evaluation Technique for Wafer-Scale Memory," IEEE Trans Jnl, Apr. 1992, pp. 19-27.
Horst, Robert W., "Task-Flow Architecture for WSI Parallel Processing," IEEE Trans Jnl, Apr. 1992, pp. 10-18.
Ganapathy et al., "Yield Optimization in Large RAM's with Hierachical Redundancy," IEEE Jnl of Solid-State Circuits, vol. 26, No. 9, Sep., 1991, pp. 1259-1269.
Aubusson, Russell C. and Ivor Catt, "Wafer-Scale Integration--A Fault-Tolerant Procedure," IEE Jnl of Solid State Circuits, vol. SC-13, No. 3, Jun., 1978, pp. 339-344.
Stodieck, Robert, "Designing With the IDT49C460 and IDT39C60 Error Detection and Correction Units," Application Note AN-24 by IDT, 1989, pp. 1-10.
Antola et al., "Reconfiguration of Binary Trees: The Flow-Driven Approach," 1991 International Conference on Wafer Scale Integration, 1991, pp. 141-147.
Shi, Weiping and W. Kent Fuchs, "Large Area Defect-Tolerant Tree Architectures," 1991 International Conference on Wafer Scale Integration, 1991, pp. 127-133.
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Oct. 1989, New York, pp. 423-425.
IBM Technical Disclosure Bulletin, vol. 32, No. 9A, Feb. 1990, New York, pp. 405-406.
Hsu Fu-Chieh
Lee Winston
Leung Wingyu
Hoffman E. Eric
Hudspeth David R.
Klivans Norman R.
Monolithic System Technology, Inc.
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